rohd library Null safety

Copyright (C) 2021-2022 Intel Corporation SPDX-License-Identifier: BSD-3-Clause

Classes

Add
A two-input addition module.
And2Gate
A two-input AND gate.
AndUnary
A unary AND gate.
ARShift
An arithmetic right-shift module.
BusSubset
A Module which gives access to a subset range of signals of the input.
Case
A block of CaseItems where only the one with a matching CaseItem.value is executed.
CaseItem
Represents a single case within a Case block.
CaseZ
A special version of Case which can do wildcard matching via z in the expression.
Combinational
Represents a block of combinational logic.
Conditional
Represents an some logical assignments or actions that will only happen under certain conditions.
ConditionalAssign
An assignment that only happens under certain conditions.
Const
Represents a Logic that never changes value.
Divide
A two-input divison module.
Else
A conditional block to execute only if condition is satisified.
ElseIf
A conditional block to execute only if condition is satisified.
Equals
A two-input equality comparison module.
ExternalSystemVerilogModule
Represents a Module whose definition exists outside of this framework in SystemVerilog.
FlipFlop
Represents a single flip-flop with no reset.
GreaterThan
A two-input comparison module for greater-than.
GreaterThanOrEqual
A two-input comparison module for greater-than-or-equal-to.
If
Represents a block of code to be conditionally executed, like if/else.
IfBlock
Represents a chain of blocks of code to be conditionally executed, like if/else if/else.
IndexGate
A two-input bit index gate Module.
Interface<TagType>
Represents a logical interface to a Module.
LessThan
A two-input comparison module for less-than.
LessThanOrEqual
A two-input comparison module for less-than-or-equal-to.
Logic
Represents a logical signal of any width which can change values.
LogicValue
An immutable 4-value representation of an arbitrary number of bits.
LogicValueChanged
Represents the event of a Logic changing value.
LShift
A logical left-shift module.
Module
Represents a synthesizable hardware entity with clearly defined interface boundaries.
Modulo
A two-input modulo module.
Multiply
A two-input multiplication module.
Mux
A mux (multiplexer) module.
NotGate
A gate Module that performs bit-wise inversion.
Or2Gate
A two-input OR gate.
OrUnary
A unary OR gate.
Pipeline
A simple pipeline, separating arbitrary combinational logic by flop stages.
PipelineStageInfo
Information and accessors associated with a Pipeline stage.
Port
An extension of Logic useful for Interface definitions.
ReadyValidPipeline
A pipeline that implements Ready/Valid protocol at each stage.
ReplicationOp
A Replication Operator Module.
RShift
A logical right-shift module.
Sequential
Represents a block of sequential logic.
SimpleClockGenerator
A very simple clock generator. Generates a non-synthesizable SystemVerilog representation.
Simulator
A functional event-based static simulator for logic behavior.
State<StateIdentifier>
Simple class to initialize each state of the FSM.
StateMachine<StateIdentifier>
Simple class for FSM StateMachine.
Subtract
A two-input subtraction module.
Swizzle
A Module that performs concatenation of signals into one bigger Logic.
SynthBuilder
A generic class which can convert a module into a generated output using a Synthesizer.
SynthesisResult
An object representing the output of a Synthesizer
Synthesizer
An object capable of converting a module into some new output format
SystemVerilogSynthesizer
A Synthesizer which generates equivalent SystemVerilog as the given Module.
WaveDumper
A waveform dumper for simulations.
Xor2Gate
A two-input XOR gate.
XorUnary
A unary XOR gate.

Mixins

CustomSystemVerilog
Allows a Module to define a custom implementation of SystemVerilog to be injected in generated output instead of instantiating a separate module.
InlineSystemVerilog
Allows a Module to define a special type of CustomSystemVerilog which can be inlined within other SystemVerilog code.

Extensions

BigLogicValueBigIntUtilities
Extends BigInt with utility functions that are useful for dealing with large bit vectors and conversion between types.
LogicSwizzle
Allows lists of Logics to be swizzled.
LogicValueSwizzle
Allows lists of LogicValues to be swizzled.

Functions

bin(String s) int
Converts a binary String representation to a binary int.
mux(Logic control, Logic d1, Logic d0) Logic
Performs a multiplexer/ternary operation.
rswizzle(List<Logic> signals) Logic
Performs a concatenation operation on the list of signals, where index 0 of signals is the least significant bit(s).
@Deprecated('Use `List<Logic>.rswizzle()` instead')
swizzle(List<Logic> signals) Logic
Performs a concatenation operation on the list of signals, where index 0 of signals is the most significant bit(s).
@Deprecated('Use `List<Logic>.swizzle()` instead')

Enums

ConditionalType
Controls characteristics about Case blocks.
SimulatorPhase
An enum for the various phases of the Simulator.

Typedefs

Dumper = WaveDumper
Deprecated: use WaveDumper instead.
@Deprecated('Use WaveDumper instead')
ExternalModule = ExternalSystemVerilogModule
Deprecated - Use ExternalSystemVerilogModule instead.
@Deprecated('Use ExternalSystemVerilogModule instead.')
FF = Sequential
Deprecated: use Sequential instead.
@Deprecated('Use Sequential instead')
Iff = ElseIf
A conditional block to execute only if condition is satisified.
LogicValues = LogicValue
Deprecated: use LogicValue instead.
@Deprecated('Use `LogicValue` instead.' ' `LogicValues` and `LogicValue` have been merged into one type.')