rohd
library
Classes
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Add
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A two-input addition module.
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And2Gate
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A two-input AND gate.
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AndUnary
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A unary AND gate.
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ARShift
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An arithmetic right-shift module.
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BusSubset
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A Module which gives access to a subset range of signals of the input.
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Case
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A block of CaseItems where only the one with a matching CaseItem.value
is executed.
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CaseItem
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Represents a single case within a Case block.
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CaseZ
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A special version of Case which can do wildcard matching via
z in
the expression.
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Combinational
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Represents a block of combinational logic.
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Conditional
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Represents an some logical assignments or actions that will only happen
under certain conditions.
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ConditionalAssign
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An assignment that only happens under certain conditions.
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ConditionalGroup
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Represents a group of Conditionals to be executed.
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Const
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Represents a Logic that never changes value.
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Divide
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A two-input divison module.
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Else
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A conditional block to execute only if condition is satisified.
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ElseIf
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A conditional block to execute only if condition is satisified.
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Equals
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A two-input equality comparison module.
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ExternalSystemVerilogModule
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Represents a Module whose definition exists outside of this framework
in SystemVerilog.
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FiniteStateMachine<StateIdentifier>
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Simple class for FSM FiniteStateMachine.
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FlipFlop
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Represents a single flip-flop with no reset.
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GreaterThan
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A two-input comparison module for greater-than.
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GreaterThanOrEqual
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A two-input comparison module for greater-than-or-equal-to.
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If
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Represents a chain of blocks of code to be conditionally executed, like
if/else if/else.
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IfBlock
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Represents a chain of blocks of code to be conditionally executed, like
if/else if/else.
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IndexGate
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A two-input bit index gate Module.
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Interface<TagType>
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Represents a logical interface to a Module.
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LessThan
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A two-input comparison module for less-than.
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LessThanOrEqual
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A two-input comparison module for less-than-or-equal-to.
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Logic
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Represents a logical signal of any width which can change values.
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LogicArray
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Represents a multi-dimensional array structure of independent Logics.
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LogicNet
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Represents a Logic which can be have multiple drivers, supporting
bidirectional signals.
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LogicStructure
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Collects a group of Logic signals into one entity which can be manipulated
in a similar way as an individual Logic.
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LogicValue
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An immutable 4-value representation of an arbitrary number of bits.
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LogicValueChanged
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Represents the event of a Logic changing value.
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LShift
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A logical left-shift module.
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Module
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Represents a synthesizable hardware entity with clearly defined interface
boundaries.
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Modulo
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A two-input modulo module.
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Multiply
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A two-input multiplication module.
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Mux
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A mux (multiplexer) module.
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NotEquals
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A two-input inequality comparison module.
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NotGate
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A gate Module that performs bit-wise inversion.
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Or2Gate
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A two-input OR gate.
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OrUnary
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A unary OR gate.
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PairInterface
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A simplified version of Interface which is intended for a common situation
where two components are communicating with each other and may share some
common inputs.
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Pipeline
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A simple pipeline, separating arbitrary combinational logic by flop stages.
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PipelineStageInfo
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Information and accessors associated with a Pipeline stage.
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Port
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An extension of Logic which performs some additional validation for
inputs and outputs of Modules.
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Power
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A two-input power module.
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ReadyValidPipeline
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A pipeline that implements Ready/Valid protocol at each stage.
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ReplicationOp
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A Replication Operator Module.
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RShift
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A logical right-shift module.
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Sequential
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Represents a block of sequential logic.
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SimpleClockGenerator
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A very simple clock generator. Generates a non-synthesizable SystemVerilog
representation.
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Simulator
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A functional event-based static simulator for logic behavior.
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State<StateIdentifier>
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Simple class to initialize each state of the FSM.
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Subtract
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A two-input subtraction module.
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Swizzle
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A Module that performs concatenation of signals into one bigger Logic.
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SynthBuilder
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A generic class which can convert a module into a generated output using
a Synthesizer.
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SynthesisResult
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An object representing the output of a Synthesizer
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Synthesizer
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An object capable of converting a module into some new output format
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SystemVerilogParameterDefinition
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Represents the definition of a SystemVerilog parameter at the time of
declaration of a module definition.
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SystemVerilogSynthesizer
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A Synthesizer which generates equivalent SystemVerilog as the
given Module.
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TriStateBuffer
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A tri-state buffer: can drive 0, 1, or leave the output floating.
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WaveDumper
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A waveform dumper for simulations.
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Xor2Gate
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A two-input XOR gate.
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XorUnary
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A unary XOR gate.
Mixins
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CustomSystemVerilog
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Allows a Module to define a custom implementation of SystemVerilog to be
injected in generated output instead of instantiating a separate
module.
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InlineSystemVerilog
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Allows a Module to define a special type of SystemVerilog which can be
inlined within other SystemVerilog code.
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SystemVerilog
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Allows a Module to control the instantiation and/or definition of
generated SystemVerilog for that module.
Functions
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bin(String s)
→ int
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Converts a binary String representation to a binary int.
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cases(Logic expression, Map conditions, {int? width, ConditionalType conditionalType = ConditionalType.none, dynamic defaultValue})
→ Logic
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Shorthand for a Case inside a Conditional block.
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flop(Logic clk, Logic d, {Logic? en, Logic? reset, dynamic resetValue, bool asyncReset = false})
→ Logic
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Constructs a positive edge triggered flip flop on
clk.
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mux(Logic control, Logic d1, Logic d0)
→ Logic
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Performs a multiplexer/ternary operation.
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rswizzle(List<Logic> signals)
→ Logic
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Performs a concatenation operation on the list of signals, where index 0 of
signals is the least significant bit(s).
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swizzle(List<Logic> signals)
→ Logic
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Performs a concatenation operation on the list of signals, where index 0 of
signals is the most significant bit(s).