LogicArray class
Represents a multidimensional array structure of independent Logics.
 Inheritance

 Object
 LogicStructure
 LogicArray
Constructors

LogicArray(List<
int> dimensions, int elementWidth, {String? name, int numUnpackedDimensions = 0}) 
Creates an array with specified
dimensions
andelementWidth
namedname
.factory 
LogicArray.port(String name, [List<
int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0]) 
Constructs a new LogicArray with a more convenient constructor signature
for when many ports in an interface are declared together. Also performs
some basic checks on the legality of the array as a port of a Module.
factory
Properties
 arrayIndex → int?

If this is a part of a LogicArray, the index within that array.
Othwerise, returns
null
.readonlyinherited  bit → LogicValue

The current active value of this signal if it has width 1, as
a LogicValue.
readonlyinherited

changed
→ Stream<
LogicValueChanged> 
A Stream of
LogicValueChanged
events which triggers at most once per Simulator tick, iff the value of the Logic has changed.readonlyinherited 
dimensions
→ List<
int> 
The number of elements at each level of the array, starting from the most
significant outermost level.
final

dstConnections
→ Iterable<
Logic> 
An Iterable of all
Logic
s that are being directly driven bythis
.latefinalinherited 
elements
→ List<
Logic> 
All elements of this structure.
latefinalinherited
 elementWidth → int

The width of leaf elements in this array.
final

glitch
→ SynchronousEmitter<
LogicValueChanged> 
A stream of
LogicValueChanged
events for every time the signal transitions at any time during a Simulator tick.readonlyinherited  hashCode → int

The hash code for this object.
readonlyinherited
 isArrayMember → bool

True if this is a member of a LogicArray.
readonlyinherited
 isInput → bool

Returns true iff this signal is an input of its parent Module.
readonlyinherited
 isOutput → bool

Returns true iff this signal is an output of its parent Module.
readonlyinherited
 isPort → bool

Returns true iff this signal is an input or output of its parent Module.
readonlyinherited

leafElements
→ List<
Logic> 
A list of all leaflevel elements at the deepest hierarchy of this
structure provided in index order.
latefinalinherited
 name → String

The name of this signal.
finalinherited

negedge
→ Stream<
LogicValueChanged> 
A Stream of
LogicValueChanged
events which triggers at most once per Simulator tick, iff the value of the Logic has changed from1
to0
.readonlyinherited 
nextChanged
→ Future<
LogicValueChanged> 
Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick.
readonlyinherited

nextNegedge
→ Future<
LogicValueChanged> 
Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick from
1
to0
.readonlyinherited 
nextPosedge
→ Future<
LogicValueChanged> 
Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick from
0
to1
.readonlyinherited  numUnpackedDimensions → int

The number of dimensions which should be treated as "unpacked", starting
from the outermost (first) elements of dimensions.
final
 packed → Logic

Packs all elements into one flattened bus.
latefinalinherited
 parentModule ↔ Module?

The Module that this Logic exists within.
read / writeinherited
 parentStructure → LogicStructure?

If this is a part of a LogicStructure, the structure which this is
a part of. Otherwise,
null
.readonlyinherited 
posedge
→ Stream<
LogicValueChanged> 
A Stream of
LogicValueChanged
events which triggers at most once per Simulator tick, iff the value of the Logic has changed from0
to1
.readonlyinherited  previousValue → LogicValue?

The value of this signal before the most recent Simulator.tick had
completed. It will be
null
before the first tick after this signal is created.readonlyinherited  reversed → Logic

Returns a version of this Logic with the bit order reversed.
readonlyinherited
 runtimeType → Type

A representation of the runtime type of the object.
readonlyinherited
 srcConnection → Logic?

A LogicStructure never has a direct source driving it, only its
elements do, so always returns
null
.readonlyinherited  structureName → String

Returns the name relative to the parentStructuredefined hierarchy, if
one exists. Otherwise, this is the same as name.
readonlyinherited
 value → LogicValue

The current active value of this signal.
readonlyinherited
 valueBigInt → BigInt

The current valid active value of this signal as a BigInt.
readonlyinherited
 valueInt → int

The current valid active value of this signal as an int.
readonlyinherited
 width → int

The number of bits in this signal.
latefinalinherited
Methods

and(
) → Logic 
Unary AND.
inherited

clone(
{String? name}) → LogicArray 
Creates a new LogicArray which has the same dimensions,
elementWidth, numUnpackedDimensions as
this
.override 
decr(
{Logic s(Logic p1)?, dynamic val = 1}) → Conditional 
Decrements each element of elements using Logic.decr.
inherited

divAssign(
dynamic val, {Logic s(Logic p1)?}) → Conditional 
Divideassigns each element of elements using Logic.divAssign.
inherited

eq(
dynamic other) → Logic 
Logical equality.
inherited

getRange(
int startIndex, [int? endIndex]) → Logic 
Returns a subset Logic. It is inclusive of
startIndex
, exclusive ofendIndex
.inherited 
gets(
Logic other) → void 
Connects this Logic directly to
other
.inherited 
gt(
dynamic other) → Logic 
Greaterthan.
inherited

gte(
dynamic other) → Logic 
Greaterthanorequalto.
inherited

hasValidValue(
) → bool 
Returns
true
iff the value of this signal is valid (nox
orz
).inherited 
incr(
{Logic s(Logic p1)?, dynamic val = 1}) → Conditional 
Increments each element of elements using Logic.incr.
inherited

inject(
dynamic val, {bool fill = false}) → void 
Injects a value onto this signal in the current Simulator tick.
inherited

isFloating(
) → bool 
Returns
true
iff all bits of the current value are floating (z
).inherited 
isIn(
List list) → Logic 
Returns
1
(of width=1) if the Logic calling this function is inlist
. Else0
(of width=1) if not present.inherited 
lt(
dynamic other) → Logic 
Lessthan.
inherited

lte(
dynamic other) → Logic 
Lessthanorequalto.
inherited

makeUnassignable(
) → void 
Makes it so that this signal cannot be assigned by any full (
<=
) or conditional (<
) assignment.inherited 
mulAssign(
dynamic val, {Logic s(Logic p1)?}) → Conditional 
Multiplyassigns each element of elements using Logic.mulAssign.
inherited

neq(
dynamic other) → Logic 
Logical inequality.
inherited

noSuchMethod(
Invocation invocation) → dynamic 
Invoked when a nonexistent method or property is accessed.
inherited

or(
) → Logic 
Unary OR.
inherited

pow(
dynamic exponent) → Logic 
Power operation
inherited

put(
dynamic val, {bool fill = false}) → void 
Puts a value
val
onto this signal, which may or may not be picked up for changed in this Simulator tick.inherited 
replicate(
int multiplier) → Logic 
Returns a replicated signal using ReplicationOp with new
width = this.width *
multiplier
The inputmultiplier
cannot be negative or 0; an exception will be thrown, otherwise.inherited 
signExtend(
int newWidth) → Logic 
Returns a new Logic with width
newWidth
where new bits added are sign bits as the most significant bits. The sign is determined using two's complement, so it takes the most significant bit of the original signal and extends with that.inherited 
slice(
int endIndex, int startIndex) → Logic 
Accesses a subset of this signal from
startIndex
toendIndex
, both inclusive.inherited 
toString(
) → String 
A string representation of this object.
override

withSet(
int startIndex, Logic update) → Logic 
Returns a copy of this Logic with the bits starting from
startIndex
up untilstartIndex
+update
.width
set toupdate
instead of their original value.inherited 
xor(
) → Logic 
Unary XOR.
inherited

zeroExtend(
int newWidth) → Logic 
Returns a new Logic with width
newWidth
where new bits added are zeros as the most significant bits.inherited
Operators

operator %(
dynamic other) → Logic 
Modulo operation.
inherited

operator &(
Logic other) → Logic 
Logical bitwise AND.
inherited

operator *(
dynamic other) → Logic 
Multiplication.
inherited

operator +(
dynamic other) → Logic 
Addition.
inherited

operator (
dynamic other) → Logic 
Subtraction.
inherited

operator /(
dynamic other) → Logic 
Division.
inherited

operator <(
dynamic other) → Conditional 
Conditional assignment operator.
inherited

operator <<(
dynamic other) → Logic 
Logical leftshift.
inherited

operator <=(
Logic other) → void 
Connects this Logic directly to another Logic.
inherited

operator ==(
Object other) → bool 
The equality operator.
inherited

operator >(
dynamic other) → Logic 
Greaterthan.
inherited

operator >=(
dynamic other) → Logic 
Greaterthanorequalto.
inherited

operator >>(
dynamic other) → Logic 
Arithmetic rightshift.
inherited

operator >>>(
dynamic other) → Logic 
Logical rightshift.
inherited

operator [](
dynamic index) → Logic 
Accesses the
index
th bit of this signal.inherited 
operator ^(
Logic other) → Logic 
Logical bitwise XOR.
inherited

operator (
Logic other) → Logic 
Logical bitwise OR.
inherited

operator ~(
) → Logic 
Logical bitwise NOT.
inherited