Swizzle class

A Module that performs concatenation of signals into one bigger Logic.

The concatenation occurs such that index 0 of signals is the most significant bit(s).

You can use convenience functions swizzle() or rswizzle() to more easily use this Module.

Inheritance

Object
Module
Swizzle

Mixed in types

InlineSystemVerilog

Constructors

Swizzle(List<Logic> signals, {String name = 'swizzle'}): Constructs a Module which concatenates signals into one large out.

Properties

definitionName → String: The definition name of this Module used when instantiating instances in generated code.
read-onlyinherited
hasBuilt → bool: Indicates whether this Module has had the build() method called on it.
read-onlyinherited
hashCode → int: The hash code for this object.
read-onlyinherited
inputs → Map<String, Logic>: A map from input port names to this Module to corresponding Logic signals.
read-onlyinherited
internalSignals → Iterable<Logic>: An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
read-onlyinherited
name → String: The name of this Module.
finalinherited
out → Logic: The output port containing concatenated signals.
latefinal
outputs → Map<String, Logic>: A map from output port names to this Module to corresponding Logic signals.
read-onlyinherited
parent → Module?: The parent Module of this Module.
read-onlyinherited
reserveDefinitionName → bool: If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
finalinherited
reserveName → bool: If true, guarantees uniqueInstanceName matches name or else the build will fail.
finalinherited
runtimeType → Type: A representation of the runtime type of the object.
read-onlyinherited
signals → Iterable<Logic>: An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
read-onlyinherited
subModules → Iterable<Module>: An Iterable of all Modules contained within this Module.
read-onlyinherited
uniqueInstanceName → String: If this module has a parent, after build this will be a guaranteed unique name within its scope.
read-onlyinherited

Methods

addInput(String name, Logic x, {int width = 1}) → Logic: Registers a signal as an input to this Module and returns an input port that can be consumed.
inherited
addInputArray(String name, Logic x, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an input LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addOutput(String name, {int width = 1}) → Logic: Registers an output to this Module and returns an output port that can be driven.
inherited
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
build() → Future<void>: Builds the Module and all subModules within it.
inherited
generateSynth() → String: Returns a synthesized version of this Module.
inherited
hierarchy() → Iterable<Module>: Returns an Iterable of Modules representing the hierarchical path to this Module.
inherited
hierarchyString([int indent = 0]) → String: Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
inlineVerilog(Map<String, String> inputs) → String: Generates custom SystemVerilog to be injected in place of the output port's corresponding signal name.
override
input(String name) → Logic: Accesses the Logic associated with this Modules input port named name.
inherited
instantiationVerilog(String instanceType, String instanceName, Map<String, String> inputs, Map<String, String> outputs) → String: Generates custom SystemVerilog to be injected in place of a module instantiation.
inherited
isInput(Logic net) → bool: Returns true iff net is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic net) → bool: Returns true iff net is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic net) → bool: Returns true iff net is the same Logic as an input or output port of this Module with the same name.
inherited
noSuchMethod(Invocation invocation) → dynamic: Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic: Accesses the Logic associated with this Modules output port named name.
inherited
toString() → String: A string representation of this object.
inherited
tryInput(String name) → Logic?: Provides the input named name if it exists, otherwise null.
inherited
tryOutput(String name) → Logic?: Provides the output named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool: The equality operator.
inherited