CaseZ class
A special version of Case which can do wildcard matching via z in
the expression.
Any z in the value of a CaseItem will act as a wildcard.
Does not support SystemVerilog's ? syntax, which is exactly functionally
equivalent to z syntax.
- Inheritance
-
- Object
- Conditional
- Case
- CaseZ
Constructors
-
CaseZ(Logic expression, List<
CaseItem> items, {List<Conditional> ? defaultItem, ConditionalType conditionalType = ConditionalType.none}) -
Whenever an item in
itemsmatchesexpression, it will be executed, but the definition of matches allows forzto be a wildcard.
Properties
- caseType → String
-
Returns the SystemVerilog keyword to represent this case block.
no setteroverride
-
conditionals
→ List<
Conditional> -
Lists of all
Conditionals directly contained within thisConditional(not including itself).latefinalinherited - conditionalType → ConditionalType
-
The type of case block this is, for special attributes
(e.g. ConditionalType.unique, ConditionalType.priority).
finalinherited
-
defaultItem
→ List<
Conditional> ? -
The default to execute when there was no match with any other CaseItems.
no setterinherited
-
drivers
→ List<
Logic> -
Lists all drivers, recursively including all sub-Conditionals drivers.
latefinalinherited
- expression → Logic
-
A logical signal to match against.
finalinherited
- hashCode → int
-
The hash code for this object.
no setterinherited
-
items
→ List<
CaseItem> -
An ordered collection of CaseItems to search through for a match
to expression.
finalinherited
-
portTypePairs
→ Map<
Logic, Logic> -
Type references for this conditional's own input uses.
no setterinherited
-
receivers
→ List<
Logic> -
Lists all receivers, recursively including all sub-Conditionals
receivers.
latefinalinherited
- runtimeType → Type
-
A representation of the runtime type of the object.
no setterinherited
Methods
-
calculateReceivers(
) → List< Logic> -
The same as receivers, but uncached for situations where the list of
conditionals may still be modified or to compute the cached result
for receivers itself.
inherited
-
driverInput(
Logic driver) → Logic -
Gets the input port associated with
driver.inherited -
driverValue(
Logic driver) → LogicValue -
Gets the value that should be used for execution for the input port
associated with
driver.inherited -
driveX(
Set< Logic> ? drivenSignals) → void -
Drives X to all receivers.
inherited
-
execute(
Set< Logic> ? drivenSignals, [void guard(Logic)?]) → void -
Executes the functionality of this Conditional and
populates
drivenSignalswith all Logics that were driven during execution.inherited -
isMatch(
LogicValue value, LogicValue expressionValue) → bool -
Returns true iff
valuematches the expressions current value.override -
noSuchMethod(
Invocation invocation) → dynamic -
Invoked when a nonexistent method or property is accessed.
inherited
-
processSsa(
Map< Logic, Logic> currentMappings, {required int context}) → Map<Logic, Logic> -
Given existing
currentMappings, connects drivers and receivers accordingly toSsaLogics and returns an updated set of mappings.inherited -
receiverOutput(
Logic receiver) → Logic -
Gets the output port associated with
receiver.inherited -
shouldPropagateType(
Logic reference, LogicValue? constantValue) → bool -
Whether synthesis should apply
reference's resolved type to this use.override -
toString(
) → String -
A string representation of this object.
inherited
-
verilogContents(
int indent, Map< String, String> inputsNameMap, Map<String, String> outputsNameMap, String assignOperator) → String -
Returns a String of SystemVerilog to be used in generated output.
inherited
Operators
-
operator ==(
Object other) → bool -
The equality operator.
inherited