NotEquals class
A two-input inequality comparison module.
Constructors
Properties
- definitionName → String
-
The definition name of this Module used when instantiating instances in
generated code.
no setterinherited
-
definitionParameters
→ List<
SystemVerilogParameterDefinition> ? -
A collection of SystemVerilog
SystemVerilogParameterDefinition
s to be declared on the definition when generating SystemVerilog for this Module if generatedDefinitionType is DefinitionGenerationType.standard.no setterinherited -
expressionlessInputs
→ List<
String> -
A list of names of inputs which should not have any SystemVerilog
expressions (including constants) in-lined into them. Only signal names
will be fed into these.
finalinherited
- generatedDefinitionType → DefinitionGenerationType
-
What kind of SystemVerilog definition this Module generates, or whether
it does at all.
no setterinherited
- hasBuilt → bool
-
Indicates whether this Module has had the build method called on it.
no setterinherited
- hashCode → int
-
The hash code for this object.
no setterinherited
-
inOuts
→ Map<
String, Logic> -
A map from inOut port names to this Module to corresponding
Logic
signals.no setterinherited -
inputs
→ Map<
String, Logic> -
A map from input port names to this Module to corresponding
Logic
signals.no setterinherited -
internalSignals
→ Iterable<
Logic> -
An Iterable of all
Logic
s contained within this Module which are not an input or output port of this Module.no setterinherited - name → String
-
The name of this Module.
finalinherited
- out → Logic
-
The output of this gate.
latefinalinherited
-
outputs
→ Map<
String, Logic> -
A map from output port names to this Module to corresponding
Logic
signals.no setterinherited - parent → Module?
-
The parent Module of this Module.
no setterinherited
- reserveDefinitionName → bool
-
If true, guarantees definitionName is maintained by a Synthesizer,
or else it will fail.
finalinherited
- reserveName → bool
-
If true, guarantees uniqueInstanceName matches name or else the
build will fail.
finalinherited
- resultSignalName → String
-
The name of the output (or inOut) port which can be the in-lined
symbol.
no setterinherited
- runtimeType → Type
-
A representation of the runtime type of the object.
no setterinherited
-
signals
→ Iterable<
Logic> -
An Iterable of all
Logic
s contained within this Module, including inputs, outputs, and internal signals of this Module.no setterinherited -
subModules
→ Iterable<
Module> -
An Iterable of all
Module
s contained within thisModule
.no setterinherited - uniqueInstanceName → String
-
If this module has a parent, after build this will be a guaranteed
unique name within its scope.
no setterinherited
- y → Logic
-
The output of this gate.
no setterinherited
Methods
-
addInOut(
String name, Logic source, {int width = 1}) → LogicNet -
Registers a signal as an inOut to this Module and returns an inOut port
that can be consumed.
inherited
-
addInOutArray(
String name, Logic source, {List< int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray -
Registers and returns an inOut LogicArray port to this Module with
the specified
dimensions
,elementWidth
, andnumUnpackedDimensions
namedname
.inherited -
addInput(
String name, Logic source, {int width = 1}) → Logic -
Registers a signal as an input to this Module and returns an input port
that can be consumed.
inherited
-
addInputArray(
String name, Logic source, {List< int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray -
Registers and returns an input LogicArray port to this Module with
the specified
dimensions
,elementWidth
, andnumUnpackedDimensions
namedname
.inherited -
addOutput(
String name, {int width = 1}) → Logic -
Registers an output to this Module and returns an output port that
can be driven.
inherited
-
addOutputArray(
String name, {List< int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray -
Registers and returns an output LogicArray port to this Module with
the specified
dimensions
,elementWidth
, andnumUnpackedDimensions
namedname
.inherited -
build(
) → Future< void> -
Builds the Module and all subModules within it.
inherited
-
definitionVerilog(
String definitionType) → String? -
A custom SystemVerilog definition to be produced for this Module.
inherited
-
generateSynth(
) → String -
Returns a synthesized version of this Module.
inherited
-
hierarchy(
) → Iterable< Module> -
Returns an Iterable of Modules representing the hierarchical path to
this Module.
inherited
-
hierarchyString(
[int indent = 0]) → String -
Returns a pretty-print String of the heirarchy of all Modules within
this Module.
inherited
-
inlineVerilog(
Map< String, String> inputs) → String -
Generates custom SystemVerilog to be injected in place of the output
port's corresponding signal name.
inherited
-
inOut(
String name) → Logic -
Accesses the Logic associated with this Modules inOut port
named
name
.inherited -
inOutSource(
String name) → Logic -
The original
source
provided to the creation of the inOut portname
via addInOut or addInOutArray.inherited -
input(
String name) → Logic -
Accesses the Logic associated with this Modules input port
named
name
.inherited -
inputSource(
String name) → Logic -
The original
source
provided to the creation of the input portname
via addInput or addInputArray.inherited -
instantiationVerilog(
String instanceType, String instanceName, Map< String, String> ports) → String -
Generates custom SystemVerilog to be injected in place of a
module
instantiation.inherited -
isInOut(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as the inOut port of this Module with the same name.inherited -
isInput(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as the input port of this Module with the same name.inherited -
isOutput(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as the output port of this Module with the same name.inherited -
isPort(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as an input, output, or inOut port of this Module with the same name.inherited -
noSuchMethod(
Invocation invocation) → dynamic -
Invoked when a nonexistent method or property is accessed.
inherited
-
output(
String name) → Logic -
Accesses the Logic associated with this Modules output port
named
name
.inherited -
toString(
) → String -
A string representation of this object.
inherited
-
tryInOut(
String name) → Logic? -
Provides the inOut named
name
if it exists, otherwisenull
.inherited -
tryInput(
String name) → Logic? -
Provides the input named
name
if it exists, otherwisenull
.inherited -
tryOutput(
String name) → Logic? -
Provides the output named
name
if it exists, otherwisenull
.inherited
Operators
-
operator ==(
Object other) → bool -
The equality operator.
inherited