Properties

bit
→ LogicValue

The current active value of this signal if it has width 1, as
a LogicValue.
@
Deprecated('Use `value` instead.' ' Check `width` separately to confirm singlebit.'), readonly, inherited

changed
→ Stream<LogicValueChanged>

A Stream of
LogicValueChanged
events which triggers at most once
per Simulator tick, iff the value of the Logic has changed.
readonly, inherited

dstConnections
→ Iterable<Logic>

An Iterable of all
Logic
s that are being directly driven by this
.
readonly, inherited

glitch
→ SynchronousEmitter<LogicValueChanged>

A stream of
LogicValueChanged
events for every time the signal
transitions at any time during a Simulator tick.
readonly, inherited

hashCode
→ int

The hash code for this object.
readonly, inherited

isInput
→ bool

Returns true iff this signal is an input of its parent Module.
readonly, inherited

isOutput
→ bool

Returns true iff this signal is an output of its parent Module.
readonly, inherited

isPort
→ bool

Returns true iff this signal is an input or output of its parent Module.
readonly, inherited

name
→ String

The name of this signal.
final, inherited

negedge
→ Stream<LogicValueChanged>

A Stream of
LogicValueChanged
events which triggers at most once
per Simulator tick, iff the value of the Logic has changed
from 1
to 0
.
readonly, inherited

nextChanged
→ Future<LogicValueChanged>

Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick.
readonly, inherited

nextNegedge
→ Future<LogicValueChanged>

Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick from
1
to 0
.
readonly, inherited

nextPosedge
→ Future<LogicValueChanged>

Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick from
0
to 1
.
readonly, inherited

parentModule
↔ Module?

The Module that this Logic exists within.

posedge
→ Stream<LogicValueChanged>

A Stream of
LogicValueChanged
events which triggers at most once
per Simulator tick, iff the value of the Logic has changed
from 0
to 1
.
readonly, inherited

reversed
→ Logic

Returns a version of this Logic with the bit order reversed.
readonly, inherited

runtimeType
→ Type

A representation of the runtime type of the object.
readonly, inherited

srcConnection
→ Logic?

The Logic signal that is driving
this
, if any.
readonly, inherited

value
→ LogicValue

The current active value of this signal.
readonly, inherited

valueBigInt
→ BigInt

The current valid active value of this signal as a BigInt.
@
Deprecated('Use value.toBigInt() instead.'), readonly, inherited

valueInt
→ int

The current valid active value of this signal as an int.
@
Deprecated('Use value.toInt() instead.'), readonly, inherited

width
→ int

The number of bits in this signal.
readonly, inherited
Methods

and()
→ Logic

Unary AND.
inherited

eq(dynamic other)
→ Logic

Logical equality.
inherited

getRange(int startIndex, int endIndex)
→ Logic

Returns a subset Logic. It is inclusive of
startIndex
, exclusive of
endIndex
.
inherited

gets(Logic other)
→ void

Connects this Logic directly to
other
.
inherited

hasValidValue()
→ bool

Returns
true
iff the value of this signal is valid (no x
or z
).
inherited

inject(dynamic val, {bool fill = false})
→ void

Injects a value onto this signal in the current Simulator tick.
inherited

isFloating()
→ bool

Returns
true
iff all bits of the current value are floating (z
).
inherited

lt(dynamic other)
→ Logic

Lessthan.
inherited

lte(dynamic other)
→ Logic

Lessthanorequalto.
inherited

makeUnassignable()
→ void

Makes it so that this signal cannot be assigned by any full (
<=
) or
conditional (<
) assignment.
inherited

noSuchMethod(Invocation invocation)
→ dynamic

Invoked when a nonexistent method or property is accessed.
inherited

or()
→ Logic

Unary OR.
inherited

put(dynamic val, {bool fill = false})
→ void

Puts a value
val
onto this signal, which may or may not be picked up
for changed in this Simulator tick.
inherited

signExtend(int newWidth)
→ Logic

Returns a new Logic with width
newWidth
where new bits added are sign
bits as the most significant bits. The sign is determined using two's
complement, so it takes the most significant bit of the original signal
and extends with that.
inherited

slice(int endIndex, int startIndex)
→ Logic

Accesses a subset of this signal from
startIndex
to endIndex
,
both inclusive.
inherited

toString()
→ String

A string representation of this object.
inherited

withSet(int startIndex, Logic update)
→ Logic

Returns a copy of this Logic with the bits starting from
startIndex
up until startIndex
+ update
.width
set to update
instead
of their original value.
inherited

xor()
→ Logic

Unary XOR.
inherited

zeroExtend(int newWidth)
→ Logic

Returns a new Logic with width
newWidth
where new bits added are zeros
as the most significant bits.
inherited