Port class
An extension of Logic which performs some additional validation for inputs and outputs of Modules.
Useful for Interface definitions.
Constructors
Properties
 arrayIndex → int?

If this is a part of a LogicArray, the index within that array.
Othwerise, returns
null
.no setterinherited  bit → LogicValue

The current active value of this signal if it has width 1, as
a LogicValue.
no setterinherited

changed
→ Stream<
LogicValueChanged> 
A Stream of
LogicValueChanged
events which triggers at most once per Simulator tick, iff the value of the Logic has changed.no setterinherited 
dstConnections
→ Iterable<
Logic> 
An Iterable of all
Logic
s that are being directly driven bythis
.latefinalinherited 
elements
→ List<
Logic> 
Provides a list of logical elements within this signal.
latefinalinherited

glitch
→ SynchronousEmitter<
LogicValueChanged> 
A stream of
LogicValueChanged
events for every time the signal transitions at any time during a Simulator tick.no setterinherited  hashCode → int

The hash code for this object.
no setterinherited
 isArrayMember → bool

True if this is a member of a LogicArray.
no setterinherited
 isInput → bool

Returns true iff this signal is an input of its parent Module.
no setterinherited
 isOutput → bool

Returns true iff this signal is an output of its parent Module.
no setterinherited
 isPort → bool

Returns true iff this signal is an input or output of its parent Module.
no setterinherited
 name → String

The name of this signal.
finalinherited
 naming → Naming

Controls the naming (and renaming) preferences of this signal in generated
outputs.
finalinherited

negedge
→ Stream<
LogicValueChanged> 
A Stream of
LogicValueChanged
events which triggers at most once per Simulator tick, iff the value of the Logic has changed from1
to0
.no setterinherited 
nextChanged
→ Future<
LogicValueChanged> 
Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick.
no setterinherited

nextNegedge
→ Future<
LogicValueChanged> 
Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick from
1
to0
.no setterinherited 
nextPosedge
→ Future<
LogicValueChanged> 
Triggers at most once, the next time that this Logic changes
value at the end of a Simulator tick from
0
to1
.no setterinherited  parentModule ↔ Module?

The Module that this Logic exists within.
getter/setter pairinherited
 parentStructure → LogicStructure?

If this is a part of a LogicStructure, the structure which this is
a part of. Otherwise,
null
.no setterinherited 
posedge
→ Stream<
LogicValueChanged> 
A Stream of
LogicValueChanged
events which triggers at most once per Simulator tick, iff the value of the Logic has changed from0
to1
.no setterinherited  previousValue → LogicValue?

The value of this signal before the most recent Simulator.tick had
completed. It will be
null
before the first tick after this signal is created.no setterinherited  reversed → Logic

Returns a version of this Logic with the bit order reversed.
no setterinherited
 runtimeType → Type

A representation of the runtime type of the object.
no setterinherited
 srcConnection → Logic?

The Logic signal that is driving
this
, if any.no setterinherited  structureName → String

Returns the name relative to the parentStructuredefined hierarchy, if
one exists. Otherwise, this is the same as name.
no setterinherited
 value → LogicValue

The current active value of this signal.
no setterinherited
 valueBigInt → BigInt

The current valid active value of this signal as a BigInt.
no setterinherited
 valueInt → int

The current valid active value of this signal as an int.
no setterinherited
 width → int

The number of bits in this signal.
no setterinherited
Methods

and(
) → Logic 
Unary AND.
inherited

decr(
{Logic s(Logic)?, dynamic val = 1}) → Conditional 
Shorthand for a Conditional which decrements this by
val
.inherited 
divAssign(
dynamic val, {Logic s(Logic)?}) → Conditional 
Shorthand for a Conditional which increments this by
val
.inherited 
eq(
dynamic other) → Logic 
Logical equality.
inherited

getRange(
int startIndex, [int? endIndex]) → Logic 
Returns a subset Logic. It is inclusive of
startIndex
, exclusive ofendIndex
.inherited 
gets(
Logic other) → void 
Connects this Logic directly to
other
.inherited 
gt(
dynamic other) → Logic 
Greaterthan.
inherited

gte(
dynamic other) → Logic 
Greaterthanorequalto.
inherited

hasValidValue(
) → bool 
Returns
true
iff the value of this signal is valid (nox
orz
).inherited 
incr(
{Logic s(Logic)?, dynamic val = 1}) → Conditional 
Shorthand for a Conditional which increments this by
val
.inherited 
inject(
dynamic val, {bool fill = false}) → void 
Injects a value onto this signal in the current Simulator tick.
inherited

isFloating(
) → bool 
Returns
true
iff all bits of the current value are floating (z
).inherited 
isIn(
List list) → Logic 
Returns
1
(of width=1) if the Logic calling this function is inlist
. Else0
(of width=1) if not present.inherited 
lt(
dynamic other) → Logic 
Lessthan.
inherited

lte(
dynamic other) → Logic 
Lessthanorequalto.
inherited

makeUnassignable(
) → void 
Makes it so that this signal cannot be assigned by any full (
<=
) or conditional (<
) assignment.inherited 
mulAssign(
dynamic val, {Logic s(Logic)?}) → Conditional 
Shorthand for a Conditional which increments this by
val
.inherited 
neq(
dynamic other) → Logic 
Logical inequality.
inherited

noSuchMethod(
Invocation invocation) → dynamic 
Invoked when a nonexistent method or property is accessed.
inherited

or(
) → Logic 
Unary OR.
inherited

pow(
dynamic exponent) → Logic 
Power operation
inherited

put(
dynamic val, {bool fill = false}) → void 
Puts a value
val
onto this signal, which may or may not be picked up for changed in this Simulator tick.inherited 
replicate(
int multiplier) → Logic 
Returns a replicated signal using ReplicationOp with new
width = this.width *
multiplier
The inputmultiplier
cannot be negative or 0; an exception will be thrown, otherwise.inherited 
signExtend(
int newWidth) → Logic 
Returns a new Logic with width
newWidth
where new bits added are sign bits as the most significant bits. The sign is determined using two's complement, so it takes the most significant bit of the original signal and extends with that.inherited 
slice(
int endIndex, int startIndex) → Logic 
Accesses a subset of this signal from
startIndex
toendIndex
, both inclusive.inherited 
toString(
) → String 
A string representation of this object.
inherited

withSet(
int startIndex, Logic update) → Logic 
Returns a copy of this Logic with the bits starting from
startIndex
up untilstartIndex
+update
.width
set toupdate
instead of their original value.inherited 
xor(
) → Logic 
Unary XOR.
inherited

zeroExtend(
int newWidth) → Logic 
Returns a new Logic with width
newWidth
where new bits added are zeros as the most significant bits.inherited
Operators

operator %(
dynamic other) → Logic 
Modulo operation.
inherited

operator &(
Logic other) → Logic 
Logical bitwise AND.
inherited

operator *(
dynamic other) → Logic 
Multiplication.
inherited

operator +(
dynamic other) → Logic 
Addition.
inherited

operator (
dynamic other) → Logic 
Subtraction.
inherited

operator /(
dynamic other) → Logic 
Division.
inherited

operator <(
dynamic other) → Conditional 
Conditional assignment operator.
inherited

operator <<(
dynamic other) → Logic 
Logical leftshift.
inherited

operator <=(
Logic other) → void 
Connects this Logic directly to another Logic.
inherited

operator ==(
Object other) → bool 
The equality operator.
inherited

operator >(
dynamic other) → Logic 
Greaterthan.
inherited

operator >=(
dynamic other) → Logic 
Greaterthanorequalto.
inherited

operator >>(
dynamic other) → Logic 
Arithmetic rightshift.
inherited

operator >>>(
dynamic other) → Logic 
Logical rightshift.
inherited

operator [](
dynamic index) → Logic 
Accesses the
index
th bit of this signal.inherited 
operator ^(
Logic other) → Logic 
Logical bitwise XOR.
inherited

operator (
Logic other) → Logic 
Logical bitwise OR.
inherited

operator ~(
) → Logic 
Logical bitwise NOT.
inherited