Logic class - rohd library

Constructors

Logic({String? name, int width = 1, Naming? naming}): Constructs a new Logic named name with width bits.
Logic.port(String name, [int width = 1]): Constructs a Logic with some additional validation for ports of Modules.
factory

Properties

arrayIndex → int?: If this is a part of a LogicArray, the index within that array. Othwerise, returns null.
no setter
bit → LogicValue: The current active value of this signal if it has width 1, as a LogicValue.
no setter
changed → Stream<LogicValueChanged>: A Stream of LogicValueChanged events which triggers at most once per Simulator tick, iff the value of the Logic has changed.
no setter
dstConnections → Iterable<Logic>: An Iterable of all Logics that are being directly driven by this.
latefinal
elements → List<Logic>: Provides a list of logical elements within this signal.
latefinal
glitch → SynchronousEmitter<LogicValueChanged>: A stream of LogicValueChanged events for every time the signal transitions at any time during a Simulator tick.
no setter
hashCode → int: The hash code for this object.
no setterinherited
isArrayMember → bool: True if this is a member of a LogicArray.
no setter
isInOut → bool: Returns true iff this signal is an inOut of its parent Module.
latefinal
isInput → bool: Returns true iff this signal is an input of its parent Module.
latefinal
isNet → bool: Indicates whether this signal behaves like a LogicNet, allowing multiple drivers.
no setter
isOutput → bool: Returns true iff this signal is an output of its parent Module.
latefinal
isPort → bool: Returns true iff this signal is an input, output, or inOut of its parent Module.
latefinal
name → String: The name of this signal.
final
naming → Naming: Controls the naming (and renaming) preferences of this signal in generated outputs.
final
negedge → Stream<LogicValueChanged>: A Stream of LogicValueChanged events which triggers at most once per Simulator tick, iff the value of the Logic has changed from 1 to 0.
no setter
nextChanged → Future<LogicValueChanged>: Triggers at most once, the next time that this Logic changes value at the end of a Simulator tick.
no setter
nextNegedge → Future<LogicValueChanged>: Triggers at most once, the next time that this Logic changes value at the end of a Simulator tick from 1 to 0.
no setter
nextPosedge → Future<LogicValueChanged>: Triggers at most once, the next time that this Logic changes value at the end of a Simulator tick from 0 to 1.
no setter
parentModule ↔ Module?: The Module that this Logic exists within.
getter/setter pair
parentStructure → LogicStructure?: If this is a part of a LogicStructure, the structure which this is a part of. Otherwise, null.
no setter
posedge → Stream<LogicValueChanged>: A Stream of LogicValueChanged events which triggers at most once per Simulator tick, iff the value of the Logic has changed from 0 to 1.
no setter
previousValue → LogicValue?: The value of this signal before the most recent Simulator.tick had completed. It will be null before the first tick after this signal is created.
no setter
reversed → Logic: Returns a version of this Logic with the bit order reversed.
latefinal
runtimeType → Type: A representation of the runtime type of the object.
no setterinherited
srcConnection → Logic?: The Logic signal that is driving this, if any.
no setter
srcConnections → Iterable<Logic>: All Logics driving this, if any.
latefinal
structureName → String: Returns the name relative to the parentStructure-defined hierarchy, if one exists. Otherwise, this is the same as name.
no setter
value → LogicValue: The current active value of this signal.
no setter
valueBigInt → BigInt: The current valid active value of this signal as a BigInt.
no setter
valueInt → int: The current valid active value of this signal as an int.
no setter
width → int: The number of bits in this signal.
no setter

Methods

abs() → Logic: Calculates the absolute value of a signal, assuming that the number is a two's complement.
and() → Logic: Unary AND.
assignSubset(List<Logic> updatedSubset, {int start = 0}) → void: Performs an assignment operation on a portion this signal to be driven by updatedSubset. Each index of updatedSubset will be assigned to drive the corresponding index, plus start, of this signal.
clone({String? name}) → Logic: Makes a copy of this, optionally with the specified name, but the same width.
decr({Logic s(Logic)?, dynamic val = 1}) → Conditional: Shorthand for a Conditional which decrements this by val.
divAssign(dynamic val, {Logic s(Logic)?}) → Conditional: Shorthand for a Conditional which increments this by val.
eq(dynamic other) → Logic: Logical equality.
getRange(int startIndex, [int? endIndex]) → Logic: Returns a subset Logic. It is inclusive of startIndex, exclusive of endIndex.
gets(Logic other) → void: Connects this Logic directly to be driven by other.
gt(dynamic other) → Logic: Greater-than.
gte(dynamic other) → Logic: Greater-than-or-equal-to.
hasValidValue() → bool: Returns true iff the value of this signal is valid (no x or z).
incr({Logic s(Logic)?, dynamic val = 1}) → Conditional: Shorthand for a Conditional which increments this by val.
inject(dynamic val, {bool fill = false}) → void: Injects a value onto this signal in the current Simulator tick.
isFloating() → bool: Returns true iff all bits of the current value are floating (z).
isIn(List list) → Logic: Returns 1 (of width=1) if the Logic calling this function is in list. Else 0 (of width=1) if not present.
lt(dynamic other) → Logic: Less-than.
lte(dynamic other) → Logic: Less-than-or-equal-to.
makeUnassignable({String? reason}) → void: Makes it so that this signal cannot be assigned by any full (<=) or conditional (<) assignment.
mulAssign(dynamic val, {Logic s(Logic)?}) → Conditional: Shorthand for a Conditional which increments this by val.
named(String name, {Naming? naming}) → Logic: Makes a clone with the provided name and optionally naming, then assigns it to be driven by this.
neq(dynamic other) → Logic: Logical inequality.
noSuchMethod(Invocation invocation) → dynamic: Invoked when a nonexistent method or property is accessed.
inherited
or() → Logic: Unary OR.
pow(dynamic exponent) → Logic: Power operation
put(dynamic val, {bool fill = false}) → void: Puts a value val onto this signal, which may or may not be picked up for changed in this Simulator tick.
replicate(int multiplier) → Logic: Returns a replicated signal using ReplicationOp with new width = this.width * multiplier
selectFrom(List<Logic> busList, {Logic? defaultValue}) → Logic: Performs a Logic index based selection on an List of Logic named busList.
signExtend(int newWidth) → Logic: Returns a new Logic width width newWidth where new bits added are sign bits as the most significant bits. The sign is determined using two's complement, so it takes the most significant bit of the original signal and extends with that.
slice(int endIndex, int startIndex) → Logic: Accesses a subset of this signal from startIndex to endIndex, both inclusive.
toString() → String: A string representation of this object.
override
withSet(int startIndex, Logic update) → Logic: Returns a copy of this Logic with the bits starting from startIndex up until startIndex + update.width set to update instead of their original value.
xor() → Logic: Unary XOR.
zeroExtend(int newWidth) → Logic: Returns a new Logic with width newWidth where new bits added are zeros as the most significant bits.

Operators

operator %(dynamic other) → Logic: Modulo operation.
operator &(Logic other) → Logic: Logical bitwise AND.
operator *(dynamic other) → Logic: Multiplication.
operator +(dynamic other) → Logic: Addition.
operator -(dynamic other) → Logic: Subtraction.
operator /(dynamic other) → Logic: Division.
operator <(dynamic other) → Conditional: Conditional assignment operator.
operator <<(dynamic other) → Logic: Logical left-shift.
operator <=(Logic other) → void: Connects this Logic directly to another Logic.
operator ==(Object other) → bool: The equality operator.
inherited
operator >(dynamic other) → Logic: Greater-than.
operator >=(dynamic other) → Logic: Greater-than-or-equal-to.
operator >>(dynamic other) → Logic: Arithmetic right-shift.
operator >>>(dynamic other) → Logic: Logical right-shift.
operator [](dynamic index) → Logic: Accesses the indexth bit of this signal.
operator ^(Logic other) → Logic: Logical bitwise XOR.
operator |(Logic other) → Logic: Logical bitwise OR.
operator ~() → Logic: Logical bitwise NOT.