Module class Null safety

Represents a synthesizable hardware entity with clearly defined interface boundaries.

Any hardware to be synthesized must be contained within a Module. This construct is similar to a SystemVerilog module.

Implementers

Constructors

Module({String name = 'unnamed_module', bool reserveName = false, String? definitionName, bool reserveDefinitionName = false})
Constructs a new Module with instance name name and definition name definitionName.

Properties

definitionName String
The definition name of this Module used when instantiating instances in generated code.
read-only
hasBuilt bool
Indicates whether this Module has had the build() method called on it.
read-only
hashCode int
The hash code for this object.
read-only, inherited
inputs Map<String, Logic>
A map from input port names to this Module to corresponding Logic signals.
read-only
internalSignals Iterable<Logic>
An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
read-only
name String
The name of this Module.
final
outputs Map<String, Logic>
A map from output port names to this Module to corresponding Logic signals.
read-only
parent Module?
The parent Module of this Module.
read-only
reserveDefinitionName bool
If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
final
reserveName bool
If true, guarantees uniqueInstanceName matches name or else the build will fail.
final
runtimeType Type
A representation of the runtime type of the object.
read-only, inherited
signals Iterable<Logic>
An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
read-only
subModules Iterable<Module>
An Iterable of all Modules contained within this Module.
read-only
uniqueInstanceName String
If this module has a parent, after build this will be a guaranteed unique name within its scope.
read-only

Methods

addInput(String name, Logic x, {int width = 1}) Logic
Registers a signal as an input to this Module and returns an input port that can be consumed.
addOutput(String name, {int width = 1}) Logic
Registers an output to this Module and returns an output port that can be driven.
build() Future<void>
Builds the Module and all subModules within it.
generateSynth() String
Returns a synthesized version of this Module.
hierarchy() Iterable<Module>
Returns an Iterable of Modules representing the hierarchical path to this Module.
hierarchyString([int indent = 0]) String
Returns a pretty-print String of the heirarchy of all Modules within this Module.
input(String name) Logic
Accesses the Logic associated with this Modules input port named name.
isInput(Logic net) bool
Returns true iff net is the same Logic as the input port of this Module with the same name.
isOutput(Logic net) bool
Returns true iff net is the same Logic as the output port of this Module with the same name.
isPort(Logic net) bool
Returns true iff net is the same Logic as an input or output port of this Module with the same name.
noSuchMethod(Invocation invocation) → dynamic
Invoked when a non-existent method or property is accessed.
inherited
output(String name) Logic
Accesses the Logic associated with this Modules output port named name.
toString() String
A string representation of this object.
override

Operators

operator ==(Object other) bool
The equality operator.
inherited

Static Methods

isUnpreferred(String name) bool
Returns true iff the signal name is "unpreferred".
unpreferredName(String name) String
Makes a signal name "unpreferred" when considering between multiple possible signal names.