Module class abstract

Represents a synthesizable hardware entity with clearly defined interface boundaries.

Any hardware to be synthesized must be contained within a Module. This construct is similar to a SystemVerilog module.

Implementers

Constructors

Module({String name = 'unnamed_module', bool reserveName = false, String? definitionName, bool reserveDefinitionName = false})
Constructs a new Module with instance name name and definition name definitionName.

Properties

definitionName → String
The definition name of this Module used when instantiating instances in generated code.
no setter
hasBuilt → bool
Indicates whether this Module has had the build method called on it.
no setter
hashCode → int
The hash code for this object.
no setterinherited
hierarchicalName → String
Returns the hierarchical name of this Module with the parent hierarchy included, separated by .s, e.g. top.mid.leaf. Because it depends on hierarchy, this is only valid after build has been called.
no setter
inOuts → Map<String, Logic>
A map from inOut port names to this Module to corresponding Logic signals.
no setter
inputs → Map<String, Logic>
A map from input port names to this Module to corresponding Logic signals.
no setter
internalSignals → Iterable<Logic>
An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
no setter
name → String
The name of this Module.
final
outputs → Map<String, Logic>
A map from output port names to this Module to corresponding Logic signals.
no setter
parent → Module?
The parent Module of this Module.
no setter
reserveDefinitionName → bool
If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
final
reserveName → bool
If true, guarantees uniqueInstanceName matches name or else the build will fail.
final
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
signals → Iterable<Logic>
An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
no setter
subModules → Iterable<Module>
An Iterable of all Modules contained within this Module.
no setter
uniqueInstanceName → String
If this module has a parent, after build this will be a guaranteed unique name within its scope.
no setter

Methods

addInOut(String name, Logic source, {int width = 1}) → LogicNet
Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module.
addInOutArray(String name, Logic source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an inOut LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
addInput(String name, Logic source, {int width = 1}) → Logic
Registers a signal as an input to this Module and returns an input port that can be consumed.
addInputArray(String name, Logic source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an input LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
addInterfacePorts<InterfaceType extends Interface<TagType>, TagType extends Enum>(InterfaceType source, {Iterable<TagType>? inputTags, Iterable<TagType>? outputTags, Iterable<TagType>? inOutTags, String uniquify(String original)?}) → InterfaceType
Connects the source to this Module using Interface.connectIO and returns a copy of the source that can be used within this module.
addOutput(String name, {int width = 1}) → Logic
Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it.
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
addPairInterfacePorts<InterfaceType extends PairInterface>(InterfaceType source, PairRole role, {String uniquify(String original)?}) → InterfaceType
Connects the source to this Module using PairInterface.pairConnectIO and returns a copy of the source that can be used within this module.
addTypedInOut<LogicType extends Logic>(String name, LogicType source) → LogicType
Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
addTypedInput<LogicType extends Logic>(String name, LogicType source) → LogicType
Registers a signal as an input to this Module and returns an input port that can be consumed. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
addTypedOutput<LogicType extends Logic>(String name, LogicType logicGenerator({String name})) → LogicType
Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it. The type of the port will be LogicType and constructed via logicGenerator, which must properly update the name of the generated LogicType as well.
build() → Future<void>
Builds the Module and all subModules within it.
generateSynth() → String
Returns a synthesized version of this Module.
hierarchy() → Iterable<Module>
Returns an Iterable of Modules representing the hierarchical path to this Module.
hierarchyString([int indent = 0]) → String
Returns a pretty-print String of the heirarchy of all Modules within this Module.
inOut(String name) → Logic
Accesses the Logic associated with this Modules inOut port named name.
inOutSource(String name) → Logic
The original source provided to the creation of the inOut port name via addInOut or addInOutArray.
input(String name) → Logic
Accesses the Logic associated with this Modules input port named name.
inputSource(String name) → Logic
The original source provided to the creation of the input port name via addInput or addInputArray.
isInOut(Logic signal) → bool
Returns true iff signal is the same Logic as the inOut port of this Module with the same name.
isInput(Logic signal) → bool
Returns true iff signal is the same Logic as the input port of this Module with the same name.
isOutput(Logic signal) → bool
Returns true iff signal is the same Logic as the output port of this Module with the same name.
isPort(Logic signal) → bool
Returns true iff signal is the same Logic as an input, output, or inOut port of this Module with the same name.
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic
Accesses the Logic associated with this Modules output port named name.
toString() → String
A string representation of this object.
override
tryInOut(String name) → Logic?
Provides the inOut named name if it exists, otherwise null.
tryInput(String name) → Logic?
Provides the input named name if it exists, otherwise null.
tryOutput(String name) → Logic?
Provides the output named name if it exists, otherwise null.

Operators

operator ==(Object other) → bool
The equality operator.
inherited

Static Methods

isUnpreferred(String name) → bool
Returns true iff the signal name is "unpreferred".
unpreferredName(String name) → String
Makes a signal name "unpreferred" when considering between multiple possible signal names.