Module class abstract
Represents a synthesizable hardware entity with clearly defined interface boundaries.
Any hardware to be synthesized must be contained within a Module.
This construct is similar to a SystemVerilog module
.
- Implementers
- Add
- And2Gate
- AndUnary
- ARShift
- BusSubset
- Combinational
- Divide
- Equals
- ExternalSystemVerilogModule
- FlipFlop
- GreaterThan
- GreaterThanOrEqual
- IndexGate
- LessThan
- LessThanOrEqual
- LShift
- Modulo
- Multiply
- Mux
- NotEquals
- NotGate
- Or2Gate
- OrUnary
- Power
- ReplicationOp
- RShift
- Sequential
- SimpleClockGenerator
- Subtract
- Swizzle
- TriStateBuffer
- Xor2Gate
- XorUnary
Constructors
Properties
- definitionName → String
-
The definition name of this Module used when instantiating instances in
generated code.
no setter
- hasBuilt → bool
-
Indicates whether this Module has had the build method called on it.
no setter
- hashCode → int
-
The hash code for this object.
no setterinherited
-
inOuts
→ Map<
String, Logic> -
A map from inOut port names to this Module to corresponding
Logic
signals.no setter -
inputs
→ Map<
String, Logic> -
A map from input port names to this Module to corresponding
Logic
signals.no setter -
internalSignals
→ Iterable<
Logic> -
An Iterable of all
Logic
s contained within this Module which are not an input or output port of this Module.no setter - name → String
-
The name of this Module.
final
-
outputs
→ Map<
String, Logic> -
A map from output port names to this Module to corresponding
Logic
signals.no setter - parent → Module?
-
The parent Module of this Module.
no setter
- reserveDefinitionName → bool
-
If true, guarantees definitionName is maintained by a Synthesizer,
or else it will fail.
final
- reserveName → bool
-
If true, guarantees uniqueInstanceName matches name or else the
build will fail.
final
- runtimeType → Type
-
A representation of the runtime type of the object.
no setterinherited
-
signals
→ Iterable<
Logic> -
An Iterable of all
Logic
s contained within this Module, including inputs, outputs, and internal signals of this Module.no setter -
subModules
→ Iterable<
Module> -
An Iterable of all
Module
s contained within thisModule
.no setter - uniqueInstanceName → String
-
If this module has a parent, after build this will be a guaranteed
unique name within its scope.
no setter
Methods
-
addInOut(
String name, Logic source, {int width = 1}) → LogicNet - Registers a signal as an inOut to this Module and returns an inOut port that can be consumed.
-
addInOutArray(
String name, Logic source, {List< int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray -
Registers and returns an inOut LogicArray port to this Module with
the specified
dimensions
,elementWidth
, andnumUnpackedDimensions
namedname
. -
addInput(
String name, Logic source, {int width = 1}) → Logic - Registers a signal as an input to this Module and returns an input port that can be consumed.
-
addInputArray(
String name, Logic source, {List< int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray -
Registers and returns an input LogicArray port to this Module with
the specified
dimensions
,elementWidth
, andnumUnpackedDimensions
namedname
. -
addOutput(
String name, {int width = 1}) → Logic - Registers an output to this Module and returns an output port that can be driven.
-
addOutputArray(
String name, {List< int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray -
Registers and returns an output LogicArray port to this Module with
the specified
dimensions
,elementWidth
, andnumUnpackedDimensions
namedname
. -
build(
) → Future< void> - Builds the Module and all subModules within it.
-
generateSynth(
) → String - Returns a synthesized version of this Module.
-
hierarchy(
) → Iterable< Module> - Returns an Iterable of Modules representing the hierarchical path to this Module.
-
hierarchyString(
[int indent = 0]) → String - Returns a pretty-print String of the heirarchy of all Modules within this Module.
-
inOut(
String name) → Logic -
Accesses the Logic associated with this Modules inOut port
named
name
. -
inOutSource(
String name) → Logic -
The original
source
provided to the creation of the inOut portname
via addInOut or addInOutArray. -
input(
String name) → Logic -
Accesses the Logic associated with this Modules input port
named
name
. -
inputSource(
String name) → Logic -
The original
source
provided to the creation of the input portname
via addInput or addInputArray. -
isInOut(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as the inOut port of this Module with the same name. -
isInput(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as the input port of this Module with the same name. -
isOutput(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as the output port of this Module with the same name. -
isPort(
Logic signal) → bool -
Returns true iff
signal
is the same Logic as an input, output, or inOut port of this Module with the same name. -
noSuchMethod(
Invocation invocation) → dynamic -
Invoked when a nonexistent method or property is accessed.
inherited
-
output(
String name) → Logic -
Accesses the Logic associated with this Modules output port
named
name
. -
toString(
) → String -
A string representation of this object.
override
-
tryInOut(
String name) → Logic? -
Provides the inOut named
name
if it exists, otherwisenull
. -
tryInput(
String name) → Logic? -
Provides the input named
name
if it exists, otherwisenull
. -
tryOutput(
String name) → Logic? -
Provides the output named
name
if it exists, otherwisenull
.
Operators
-
operator ==(
Object other) → bool -
The equality operator.
inherited
Static Methods
-
isUnpreferred(
String name) → bool - Returns true iff the signal name is "unpreferred".
-
unpreferredName(
String name) → String - Makes a signal name "unpreferred" when considering between multiple possible signal names.