Sequential class Null safety

Represents a block of sequential logic.

This is similar to an always_ff block in SystemVerilog. Positive edge triggered by either one trigger or multiple with Sequential.multi.

Inheritance

Constructors

Sequential(Logic clk, List<Conditional> conditionals, {String name = 'sequential'})
Constructs a Sequential single-triggered by clk.
Sequential.multi(List<Logic> clks, List<Conditional> conditionals, {String name = 'sequential'})
Constructs a Sequential multi-triggered by any of clks.

Properties

conditionals List<Conditional>
A List of the Conditionals to execute.
final, inherited
definitionName String
The definition name of this Module used when instantiating instances in generated code.
read-only, inherited
hasBuilt bool
Indicates whether this Module has had the build() method called on it.
read-only, inherited
hashCode int
The hash code for this object.
read-only, inherited
inputs Map<String, Logic>
A map from input port names to this Module to corresponding Logic signals.
read-only, inherited
internalSignals Iterable<Logic>
An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
read-only, inherited
name String
The name of this Module.
final, inherited
outputs Map<String, Logic>
A map from output port names to this Module to corresponding Logic signals.
read-only, inherited
parent Module?
The parent Module of this Module.
read-only, inherited
reserveDefinitionName bool
If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
final, inherited
reserveName bool
If true, guarantees uniqueInstanceName matches name or else the build will fail.
final, inherited
runtimeType Type
A representation of the runtime type of the object.
read-only, inherited
signals Iterable<Logic>
An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
read-only, inherited
subModules Iterable<Module>
An Iterable of all Modules contained within this Module.
read-only, inherited
uniqueInstanceName String
If this module has a parent, after build this will be a guaranteed unique name within its scope.
read-only, inherited

Methods

addInput(String name, Logic x, {int width = 1}) Logic
Registers a signal as an input to this Module and returns an input port that can be consumed.
@protected, inherited
addOutput(String name, {int width = 1}) Logic
Registers an output to this Module and returns an output port that can be driven.
@protected, inherited
alwaysVerilogStatement(Map<String, String> inputs) String
The "always" part of the always block when generating SystemVerilog.
assignOperator() String
The assignment operator to use when generating SystemVerilog.
build() Future<void>
Builds the Module and all subModules within it.
@mustCallSuper, inherited
generateSynth() String
Returns a synthesized version of this Module.
inherited
hierarchy() Iterable<Module>
Returns an Iterable of Modules representing the hierarchical path to this Module.
inherited
hierarchyString([int indent = 0]) String
Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
input(String name) Logic
Accesses the Logic associated with this Modules input port named name.
@protected, inherited
instantiationVerilog(String instanceType, String instanceName, Map<String, String> inputs, Map<String, String> outputs) String
Generates custom SystemVerilog to be injected in place of a module instantiation.
inherited
isInput(Logic net) bool
Returns true iff net is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic net) bool
Returns true iff net is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic net) bool
Returns true iff net is the same Logic as an input or output port of this Module with the same name.
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a non-existent method or property is accessed.
inherited
output(String name) Logic
Accesses the Logic associated with this Modules output port named name.
inherited
toString() String
A string representation of this object.
inherited

Operators

operator ==(Object other) bool
The equality operator.
inherited