SystemVerilogSynthesizer class Null safety

A Synthesizer which generates equivalent SystemVerilog as the given Module.

Attempts to maintain signal naming and structure as much as possible.

Inheritance

Constructors

SystemVerilogSynthesizer()

Properties

hashCode int
The hash code for this object.
read-onlyinherited
runtimeType Type
A representation of the runtime type of the object.
read-onlyinherited

Methods

generatesDefinition(Module module) bool
Determines whether module needs a separate definition or can just be described in-line.
override
noSuchMethod(Invocation invocation) → dynamic
Invoked when a non-existent method or property is accessed.
inherited
synthesize(Module module, Map<Module, String> moduleToInstanceTypeMap) SynthesisResult
Synthesizes module into a SynthesisResult, given the mapping in moduleToInstanceTypeMap.
override
toString() String
A string representation of this object.
inherited

Operators

operator ==(Object other) bool
The equality operator.
inherited

Static Methods

instantiationVerilogWithParameters(Module module, String instanceType, String instanceName, Map<String, String> inputs, Map<String, String> outputs, {Map<String, String>? parameters, bool forceStandardInstantiation = false}) String
Creates a line of SystemVerilog that instantiates module.