SystemVerilogSynthesizer class

A Synthesizer which generates equivalent SystemVerilog as the given Module.

Attempts to maintain signal naming and structure as much as possible.

Inheritance

Constructors

SystemVerilogSynthesizer({SystemVerilogSynthesizerConfiguration configuration = const SystemVerilogSynthesizerConfiguration()})
Creates a SystemVerilog synthesizer with the specified configuration.

Properties

configuration → SystemVerilogSynthesizerConfiguration
Configuration controlling generated SystemVerilog.
final
hashCode → int
The hash code for this object.
no setterinherited
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited

Methods

generatesDefinition(Module module) → bool
Determines whether module needs a separate definition or can just be described in-line.
override
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
synthesize(Module module, String getInstanceTypeOfModule(Module module)) → SynthesisResult
Synthesizes module into a SynthesisResult, given the mapping provided by getInstanceTypeOfModule.
override
toString() → String
A string representation of this object.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited

Static Methods

instantiationVerilogFor({required Module module, required String instanceType, required String instanceName, required Map<String, String> ports, Map<String, String>? parameters, bool forceStandardInstantiation = false}) → String
Creates a line of SystemVerilog that instantiates module.
instantiationVerilogWithParameters(Module module, String instanceType, String instanceName, Map<String, String> inputs, Map<String, String> outputs, {Map<String, String> inOuts = const {}, Map<String, String>? parameters, bool forceStandardInstantiation = false}) → String
Creates a line of SystemVerilog that instantiates module.