generateSynth method
Returns a synthesized version of this Module.
Currently returns one long file in SystemVerilog, but in the future may have other output formats, languages, files, etc.
Implementation
String generateSynth() {
if (!_hasBuilt) {
throw ModuleNotBuiltException();
}
final synthHeader = '''
/**
* Generated by ROHD - www.github.com/intel/rohd
* Generation time: ${Timestamper.stamp()}
* ROHD Version: ${Config.version}
*/
''';
return synthHeader +
SynthBuilder(this, SystemVerilogSynthesizer())
.getFileContents()
.join('\n\n////////////////////\n\n');
}