instantiationVerilog method

  1. @override
String instantiationVerilog(
  1. String instanceType,
  2. String instanceName,
  3. Map<String, String> ports
)
inherited

Generates custom SystemVerilog to be injected in place of a module instantiation.

The instanceType and instanceName represent the type and name, respectively of the module that would have been instantiated had it not been overridden. ports is a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog.

If a standard instantiation is desired, either return null or use SystemVerilogSynthesizer.instantiationVerilogFor with forceStandardInstantiation set to true. By default, null is returned and thus a standard instantiation is used.

Implementation

@override
String instantiationVerilog(
  String instanceType,
  String instanceName,
  Map<String, String> ports,
) {
  // no `inouts` can be used in a `Conditional`
  final inputs = Map.fromEntries(
      ports.entries.where((element) => this.inputs.containsKey(element.key)));
  final outputs = Map.fromEntries(ports.entries
      .where((element) => this.outputs.containsKey(element.key)));

  var verilog = '';
  verilog += '//  $instanceName\n';
  verilog += '${alwaysVerilogStatement(inputs)} begin\n';
  verilog += _alwaysContents(inputs, outputs, assignOperator());
  verilog += 'end\n';
  return verilog;
}