alwaysVerilogStatement method

  1. @override
String alwaysVerilogStatement(
  1. Map<String, String> inputs
)

The "always" part of the always block when generating SystemVerilog.

For example, always_comb or always_ff.

Implementation

@override
String alwaysVerilogStatement(Map<String, String> inputs) {
  final triggers =
      _clks.map((clk) => 'posedge ${inputs[clk.name]}').join(' or ');
  return 'always_ff @($triggers)';
}