alwaysVerilogStatement method

  1. @override
String alwaysVerilogStatement(
  1. Map<String, String> inputs
)

The "always" part of the always block when generating SystemVerilog.

For example, always_comb or always_ff.

Implementation

@override
String alwaysVerilogStatement(Map<String, String> inputs) {
  final svTriggers = _triggers
      .map((trigger) =>
          '${trigger.verilogTriggerKeyword} ${inputs[trigger.signal.name]}')
      .join(' or ');
  return 'always_ff @($svTriggers)';
}