operator [] method

Accesses the indexth bit of this signal.

Accepts both int and Logic as index.

Throws Exception when index is not an int or Logic.

Negative/Positive index values are allowed (only when index is an int). When, index is a Logic, the index value is treated as an unsigned value. The negative indexing starts from the end=width-1

-(width) <= index < width

Logic nextVal = addOutput('nextVal', width: width);
// Example: val = 0xce, val.width = 8, bin(0xce) = "0b11001110"
// Positive Indexing
nextVal <= val[3]; // output: 1

// Negative Indexing
nextVal <= val[-5]; // output: 1, also val[3] == val[-5]

// Error cases
nextVal <= val[-9]; // Error!: allowed values [-8, 7]
nextVal <= val[8]; // Error!: allowed values [-8, 7]

Note: When, indexed by a Logic value, out-of-bounds will always return an invalid (LogicValue.x) value. This behavior is differs in simulation as compared to the generated SystemVerilog. In the generated SystemVerilog, index will be ignored, and the logic is returned as-is.

If isNet, then the result will also be a net.