rohd library
Classes
- Add
- A two-input addition module.
- And2Gate
- A two-input AND gate.
- AndUnary
- A unary AND gate.
- ARShift
- An arithmetic right-shift module.
- BusSubset
- A Module which gives access to a subset range of signals of the input.
- Case
- A block of CaseItems where only the one with a matching CaseItem.value is executed.
- CaseItem
- Represents a single case within a Case block.
- CaseZ
-
A special version of Case which can do wildcard matching via
zin the expression. - Combinational
- Represents a block of combinational logic.
- Conditional
- Represents an some logical assignments or actions that will only happen under certain conditions.
- ConditionalAssign
- An assignment that only happens under certain conditions.
- ConditionalGroup
- Represents a group of Conditionals to be executed.
- Const
- Represents a Logic that never changes value.
- Divide
- A two-input division module.
- Else
- A conditional block to execute only if condition is satisfied.
- ElseIf
- A conditional block to execute only if condition is satisfied.
- Equals
- A two-input equality comparison module.
- ExternalSystemVerilogModule
- Represents a Module whose definition exists outside of this framework in SystemVerilog.
-
FiniteStateMachine<
StateIdentifier> - Simple class for FSM FiniteStateMachine.
- FlipFlop
- Represents a single flip-flop with no reset.
- GreaterThan
- A two-input comparison module for greater-than.
- GreaterThanOrEqual
- A two-input comparison module for greater-than-or-equal-to.
- If
-
Represents a chain of blocks of code to be conditionally executed, like
if/else if/else. - IfBlock
-
Represents a chain of blocks of code to be conditionally executed, like
if/else if/else. - IndexGate
- A two-input bit index gate Module.
-
Interface<
TagType extends Enum> - Represents a logical interface to a Module.
- LessThan
- A two-input comparison module for less-than.
- LessThanOrEqual
- A two-input comparison module for less-than-or-equal-to.
- Logic
- Represents a logical signal of any width which can change values.
- LogicArray
- Represents a multi-dimensional array structure of independent Logics.
- LogicNet
- Represents a Logic which can be have multiple drivers, supporting bidirectional signals.
- LogicStructure
- Collects a group of Logic signals into one entity which can be manipulated in a similar way as an individual Logic.
- LogicValue
- An immutable 4-value representation of an arbitrary number of bits.
- LogicValueChanged
- Represents the event of a Logic changing value.
- LShift
- A logical left-shift module.
- Module
- Represents a synthesizable hardware entity with clearly defined interface boundaries.
- Modulo
- A two-input modulo module.
- Multiply
- A two-input multiplication module.
- Mux
- A mux (multiplexer) module.
- NotEquals
- A two-input inequality comparison module.
- NotGate
- A gate Module that performs bit-wise inversion.
- Or2Gate
- A two-input OR gate.
- OrUnary
- A unary OR gate.
- PairInterface
- A simplified version of Interface which is intended for a common situation where two components are communicating with each other and may share some common inputs.
- Pipeline
- A simple pipeline, separating arbitrary combinational logic by flop stages.
- PipelineStageInfo
- Information and accessors associated with a Pipeline stage.
- Port
- An extension of Logic which performs some additional validation for inputs and outputs of Modules.
- Power
- A two-input power module.
- ReadyValidPipeline
- A pipeline that implements Ready/Valid protocol at each stage.
- ReplicationOp
- A Replication Operator Module.
- RShift
- A logical right-shift module.
- Sequential
- Represents a block of sequential logic.
- SimpleClockGenerator
- A very simple clock generator. Generates a non-synthesizable SystemVerilog representation.
- Simulator
- A functional event-based static simulator for logic behavior.
-
State<
StateIdentifier> - Simple class to initialize each state of the FSM.
- Subtract
- A two-input subtraction module.
- Swizzle
- A Module that performs concatenation of signals into one bigger Logic.
- SynthBuilder
- A generic class which can convert a module into a generated output using a Synthesizer.
- SynthesisResult
- An object representing the output of a Synthesizer for one module.
- Synthesizer
- An object capable of converting a module into some new output format
- SynthFileContents
- Represents contents of a file.
- SystemVerilogParameterDefinition
- Represents the definition of a SystemVerilog parameter at the time of declaration of a module definition.
- SystemVerilogSynthesizer
- A Synthesizer which generates equivalent SystemVerilog as the given Module.
- SystemVerilogSynthesizerConfiguration
- Configuration for SystemVerilog synthesis.
- TriStateBuffer
- A tri-state buffer: can drive 0, 1, or leave the output floating.
- WaveDumper
- A waveform dumper for simulations.
- Xor2Gate
- A two-input XOR gate.
- XorUnary
- A unary XOR gate.
Enums
- ConditionalType
- Controls characteristics about Case blocks.
- DefinitionGenerationType
- A type of generation for generated outputs.
- Naming
- / Configuration options and utilities for naming and renaming signals.
- PairDirection
- A direction for signals between a pair of components.
- PairRole
- The role that a component in a pair plays.
- SimulatorPhase
- An enum for the various phases of the Simulator.
- SystemVerilogPortType
- Controls whether a type is included in a SystemVerilog port declaration.
Mixins
- CustomSystemVerilog
-
Allows a Module to define a custom implementation of SystemVerilog to be
injected in generated output instead of instantiating a separate
module. - InlineSystemVerilog
- Allows a Module to define a special type of SystemVerilog which can be inlined within other SystemVerilog code.
- SystemVerilog
- Allows a Module to control the instantiation and/or definition of generated SystemVerilog for that module.
Extensions
- BigLogicValueBigIntUtilities on BigInt
- Extends BigInt with utility functions that are useful for dealing with large bit vectors and conversion between types.
-
IndexedLogic
on List<
Logic> - Allows a lists of Logics to have its elemets picked by a Logic index value.
-
LogicSwizzle
on List<
Logic> - Allows lists of Logics to be swizzled.
-
LogicValueSwizzle
on List<
LogicValue> - Allows lists of LogicValues to be swizzled.
- RandLogicValue on Random
- Allows random generation of LogicValue for BigInt and int.
Functions
-
bin(
String s) → int - Converts a binary String representation to a binary int.
-
cases(
Logic expression, Map conditions, {int? width, ConditionalType conditionalType = ConditionalType.none, dynamic defaultValue}) → Logic - Shorthand for a Case inside a Conditional block.
-
flop(
Logic clk, Logic d, {Logic? en, Logic? reset, dynamic resetValue, bool asyncReset = false}) → Logic -
Constructs a positive edge triggered flip flop on
clk. -
mux(
Logic control, Logic d1, Logic d0) → Logic - Performs a multiplexer/ternary operation.
-
rswizzle(
List< Logic> signals) → Logic -
Performs a concatenation operation on the list of signals, where index 0 of
signalsis the least significant bit(s). -
swizzle(
List< Logic> signals) → Logic -
Performs a concatenation operation on the list of signals, where index 0 of
signalsis the most significant bit(s).
Typedefs
- Dumper = WaveDumper
- Deprecated: use WaveDumper instead.
- ExternalModule = ExternalSystemVerilogModule
- Deprecated - Use ExternalSystemVerilogModule instead.
- FF = Sequential
- Deprecated: use Sequential instead.
- Iff = ElseIf
-
A conditional block to execute only if
conditionis satisfied. - LogicValues = LogicValue
- Deprecated: use LogicValue instead.
-
StateMachine<
T> = FiniteStateMachine< T> - Deprecated: use FiniteStateMachine instead.
Exceptions / Errors
- EmptyReservedNameException
-
An exception that thrown when a reserved name is
null. - IllegalConfigurationException
- An exception that is thrown when somethins is configured in an illegal way.
- InterfaceNameException
- An Exception thrown when an interface has an invalid name.
- InterfaceTypeException
- An Exception thrown when an interface has an issue with its type.
- InvalidConditionalException
- An exception that is thrown when a Conditional has been constructed in an invalid way.
- InvalidHierarchyException
- An Exception thrown when a constructed hierarchy is illegal.
- InvalidMultiplierException
- An exception that thrown when a Logic is replicated with an invalid (<1) multiplier.
- InvalidPortNameException
- An exception that thrown when a port or interface name is invalid.
- InvalidReservedNameException
- An exception that thrown when a reserved name is invalid.
- InvalidTruncationException
- An exception that is thrown when a LogicValue operation couldn't be performed due invalid data truncation.
- InvalidValueOperationException
- An exception that is thrown when a given operation cannot be performed on invalid LogicValue
- LogicConstructionException
- An exception that thrown when a Logic is connecting to itself.
- LogicValueConstructionException
- An exception that thrown when a LogicValue cannot be properly constructed.
- LogicValueConversionException
- An exception that is thrown when a LogicValue cannot be properly converted.
- MappedSignalAlreadyAssignedException
- An exception that is thrown when Combinational.ssa is attempting to deduce mappings for signals but fails since a signal would be connected multiple times.
- ModuleNotBuiltException
- An Exception thrown when a Module was used in a way that required it to be built first, but it was not yet built.
- NonSupportedTypeException
-
An exception that thrown when
runtimeTypeof expected vector output fromSimCompareis invalid or unsupported. - NullReservedNameException
-
An exception that thrown when a reserved name is
null. - PortDoesNotExistException
- An Exception thrown when a port does not exist.
- PortRulesViolationException
- An Exception thrown when a port is not following the input/output rules.
- PortTypeException
- An Exception thrown when a port has the wrong type.
- PortWidthMismatchException
- An Exception thrown when a port has the wrong width.
- PutException
- An exception that thrown when a Logic signal fails to Logic.put.
- RohdException
- A base type of exception that ROHD-specific exceptions inherit from.
- SelfConnectingLogicException
- An exception that thrown when a Logic is connecting to itself.
- SignalRedrivenException
- An exception that is thrown when a Logic signal is driven multiple times.
- SignalWidthMismatchException
- An Exception thrown when a signal has the wrong width.
- SimulatorException
- An Exception thrown when an error occurs in the simulator.
- SynthException
- An Exception thrown when an error occurs in the simulator.
- UnassignableException
-
An exception that thrown when a Logic signal fails to
put. - An exception that thrown when a reserved name cannot be acquired.
- UninitializedSignalException
- An exception that is thrown when Combinational.ssa detects that an SSA signal is being used before it was initialized.
- UnsupportedTypeException
- An exception that is thrown when an unsupported type is used.
- ValueWidthMismatchException
- An exception that is thrown when LogicValues of different width are found.
- WriteAfterReadException
- An exception that is thrown when a "write after read" violation occurs.