instantiationVerilog method Null safety
override
Generates custom SystemVerilog to be injected in place of a module
instantiation.
The instanceType
and instanceName
represent the type and name,
respectively of the module that would have been instantiated had it not
been overridden. The Maps inputs
and outputs
are a mapping from the
Module's port names to the names of the signals that are passed into
those ports in the generated SystemVerilog.
Implementation
@override
String instantiationVerilog(String instanceType, String instanceName,
Map<String, String> inputs, Map<String, String> outputs) {
if (outputs.length != 1) {
throw Exception(
'Inline verilog must have exactly one output, but saw $outputs.');
}
final output = outputs.values.first;
final inline = inlineVerilog(inputs);
return 'assign $output = $inline; // $instanceName';
}