Logic constructor

Logic(
  1. {String? name,
  2. int width = 1,
  3. Naming? naming}
)

Constructs a new Logic named name with width bits.

The default value for width is 1. The name should be synthesizable to the desired output (e.g. SystemVerilog).

The naming and name, if unspecified, are chosen based on the rules in Naming.chooseNaming and Naming.chooseName, respectively.

Implementation

Logic({
  String? name,
  int width = 1,
  Naming? naming,
})  : naming = Naming.chooseNaming(name, naming),
      name = Naming.chooseName(name, naming),
      _wire = _Wire(width: width) {
  if (width < 0) {
    throw LogicConstructionException(
        'Logic width must be greater than or equal to 0.');
  }
}