instantiationVerilogWithParameters static method Null safety

String instantiationVerilogWithParameters(
  1. Module module,
  2. String instanceType,
  3. String instanceName,
  4. Map<String, String> inputs,
  5. Map<String, String> outputs,
  6. {Map<String, String>? parameters,
  7. bool forceStandardInstantiation = false}
)

Creates a line of SystemVerilog that instantiates module.

The instantiation will create it as type instanceType and name instanceName.

inputs and outputs map module input/output name to a verilog signal name. For example: To generate this SystemVerilog: sig_c = sig_a & sig_b Based on this module definition: c <= a & b The values for inputs and outputs should be: inputs: { 'a' : 'sig_a', 'b' : 'sig_b'} outputs: { 'c' : 'sig_c' }

Implementation

static String instantiationVerilogWithParameters(
    Module module,
    String instanceType,
    String instanceName,
    Map<String, String> inputs,
    Map<String, String> outputs,
    {Map<String, String>? parameters,
    bool forceStandardInstantiation = false}) {
  if (!forceStandardInstantiation) {
    if (module is CustomSystemVerilog) {
      return module.instantiationVerilog(
          instanceType, instanceName, inputs, outputs);
    }
  }

  //non-custom needs more details
  final connections = <String>[];
  module.inputs.forEach((signalName, logic) {
    connections.add('.$signalName(${inputs[signalName]})');
  });
  module.outputs.forEach((signalName, logic) {
    connections.add('.$signalName(${outputs[signalName]})');
  });
  final connectionsStr = connections.join(',');
  var parameterString = '';
  if (parameters != null) {
    final parameterContents =
        parameters.entries.map((e) => '.${e.key}(${e.value})').join(',');
    parameterString = '#($parameterContents)';
  }
  return '$instanceType $parameterString $instanceName($connectionsStr);';
}