synthesize method Null safety

  1. @override
SynthesisResult synthesize(
  1. Module module,
  2. Map<Module, String> moduleToInstanceTypeMap
)
override

Synthesizes module into a SynthesisResult, given the mapping in moduleToInstanceTypeMap.

Implementation

@override
SynthesisResult synthesize(
        Module module, Map<Module, String> moduleToInstanceTypeMap) =>
    _SystemVerilogSynthesisResult(module, moduleToInstanceTypeMap);