verilogContents method
- int indent,
- Map<
String, String> inputsNameMap, - Map<
String, String> outputsNameMap, - String assignOperator
override
Returns a String of SystemVerilog to be used in generated output.
The indent
is used for pretty-printing, and should generally be
incremented for sub-Conditionals. The inputsNameMap
and
outputsNameMap
are a mapping from port names to SystemVerilog variable
names for inputs and outputs, respectively. The assignOperator
is the
SystemVerilog operator that should be used for any assignments within
this Conditional.
Implementation
@override
String verilogContents(int indent, Map<String, String> inputsNameMap,
Map<String, String> outputsNameMap, String assignOperator) {
final padding = Conditional.calcPadding(indent);
final expressionName = inputsNameMap[driverInput(expression).name];
var caseHeader = caseType;
if (conditionalType == ConditionalType.priority) {
caseHeader = 'priority $caseType';
} else if (conditionalType == ConditionalType.unique) {
caseHeader = 'unique $caseType';
}
final verilog = StringBuffer('$padding$caseHeader ($expressionName) \n');
final subPadding = Conditional.calcPadding(indent + 2);
for (final item in items) {
final conditionName = inputsNameMap[driverInput(item.value).name];
final caseContents = item.then
.map((conditional) => conditional.verilogContents(
indent + 4, inputsNameMap, outputsNameMap, assignOperator))
.join('\n');
verilog.write('''
$subPadding$conditionName : begin
$caseContents
${subPadding}end
''');
}
if (defaultItem != null) {
final defaultCaseContents = defaultItem!
.map((conditional) => conditional.verilogContents(
indent + 4, inputsNameMap, outputsNameMap, assignOperator))
.join('\n');
verilog.write('''
${subPadding}default : begin
$defaultCaseContents
${subPadding}end
''');
}
verilog.write('${padding}endcase\n');
return verilog.toString();
}