BridgeModule class

A specialized module class that extends ROHD's Module with advanced connectivity and hierarchy management capabilities.

BridgeModule provides enhanced functionality for creating complex hardware designs, including:

Interface-based connectivity with automatic port mapping
Hierarchical port and interface punching operations
JSON-based module definition support
Parameter passing and management
SystemVerilog leaf module integration
Advanced connection routing between hierarchy levels

This class serves as the foundation for building scalable, well-connected hardware IP modules in the ROHD Bridge framework.

Inheritance

Object
Module
BridgeModule

Mixed-in types

SystemVerilog

Available extensions

Constructors

BridgeModule.new(String definitionName, {List<SystemVerilogParameterDefinition>? definitionParameters, Map<String, String>? instantiationParameters, String? name, bool reserveDefinitionName = true, bool reserveName = false, bool allowUniquification = true, bool isSystemVerilogLeaf = false}): Creates a new BridgeModule with enhanced connectivity capabilities.
BridgeModule.fromJson(Map<String, dynamic> jsonContents, {String? name, bool reserveName = false}): Creates a BridgeModule from a JSON module description.
factory

Properties

allowUniquification → bool: Controls whether port and interface names can be automatically uniquified.
final
definitionName → String: The definition name of this Module used when instantiating instances in generated code.
no setterinherited
definitionParameters → List<SystemVerilogParameterDefinition>: A collection of SystemVerilog SystemVerilogParameterDefinitions to be declared on the definition when generating SystemVerilog for this Module if generatedDefinitionType is DefinitionGenerationType.standard.
no setteroverride
expressionlessInputs → List<String>: A list of names of inputs which should not have any SystemVerilog expressions (including constants) in-lined into them. Only signal names will be fed into these.
finalinherited
generatedDefinitionType → DefinitionGenerationType: What kind of SystemVerilog definition this Module generates, or whether it does at all.
no setteroverride
hasBuilt → bool: Indicates whether this Module has had the build method called on it.
no setterinherited
hashCode → int: The hash code for this object.
no setterinherited
hierarchicalName → String: Available on Module, provided by the RohdBridgeModuleExtensions extension
Provides a full hierarchical name based on hierarchy.
no setter
inOuts → Map<String, Logic>: A map from inOut port names to this Module to corresponding Logic signals.
no setterinherited
inputs → Map<String, Logic>: A map from input port names to this Module to corresponding Logic signals.
no setterinherited
instantiationParameters → Map<String, String>: Pass-through parameters used when instantiating this module in SystemVerilog.
no setter
interfaces → Map<String, InterfaceReference<PairInterface>>: Unmodifiable map of all interfaces added to this module.
latefinal
internalSignals → Iterable<Logic>: An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
no setterinherited
isSystemVerilogLeaf → bool: Indicates whether this module represents an external SystemVerilog leaf.
final
name → String: The name of this Module.
finalinherited
outputs → Map<String, Logic>: A map from output port names to this Module to corresponding Logic signals.
no setterinherited
parent → Module?: The parent Module of this Module.
no setteroverride
renamedPorts → Map<String, String>: Internal mapping of renamed ports for backwards compatibility.
latefinal
reserveDefinitionName → bool: If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
finalinherited
reserveName → bool: If true, guarantees uniqueInstanceName matches name or else the build will fail.
finalinherited
runtimeType → Type: A representation of the runtime type of the object.
no setterinherited
signals → Iterable<Logic>: An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
no setterinherited
structMap → Map<String, PortReference>: Map of struct member names to their corresponding packed bit slice ranges.
no setter
subBridgeModules → Iterable<BridgeModule>: All submodules that are instances of BridgeModule.
no setter
subModules → Iterable<Module>: Provides access to submodules before and after the build process.
no setteroverride
uniqueInstanceName → String: If this module has a parent, after build this will be a guaranteed unique name within its scope.
no setterinherited

Methods

addFromJson(Map<String, dynamic> jsonContents) → void: Available on BridgeModule, provided by the BridgeModuleFromJson extension
Populates ports, interfaces, and parameters from JSON representing the full module.
addInOut(String name, Logic? source, {int width = 1}) → LogicNet: Adds an inOut in the same way as the base Module does.
override
addInOutArray(String name, Logic? source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Adds an inOut array in the same way as the base Module does.
override
addInput(String name, Logic? source, {int width = 1}) → Logic: Adds an input in the same way as the base Module does.
override
addInputArray(String name, Logic? source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Adds an input array port with enhanced name management.
override
addInterface<InterfaceType extends PairInterface>(InterfaceType intf, {required String name, required PairRole role, bool connect = true, bool allowNameUniquification = false, String portUniquify(String logical)?}) → InterfaceReference<InterfaceType>: Adds an interface to this module with comprehensive configuration options.
addInterfacePorts<InterfaceType extends Interface<TagType>, TagType extends Enum>(InterfaceType source, {Iterable<TagType>? inputTags, Iterable<TagType>? outputTags, Iterable<TagType>? inOutTags, String uniquify(String original)?}) → InterfaceType: Connects the source to this Module using Interface.connectIO and returns a copy of the source that can be used within this module.
inherited
addInterfacesFromJson(String instanceName, Map<String, dynamic> busInterfaces, Map<String, String> parameters) → void: Available on BridgeModule, provided by the BridgeModuleFromJson extension
Creates interfaces based on a JSON input.
addOutput(String name, {int width = 1}) → Logic: Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it.
override
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray: Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
override
addPairInterfacePorts<InterfaceType extends PairInterface>(InterfaceType source, PairRole role, {String uniquify(String original)?}) → InterfaceType: Connects the source to this Module using PairInterface.pairConnectIO and returns a copy of the source that can be used within this module.
inherited
addParametersFromJson(Map<String, dynamic> parameterList) → Map<String, String>: Available on BridgeModule, provided by the BridgeModuleFromJson extension
Adds parameters to the module from the JSON parameterList.
addPortMap(PortReference port, InterfacePortReference intfPort, {bool connect = false}) → PortMap: Creates a mapping between a module port and an interface port.
addPortsFromJson(List portInfo, Map<String, String> parameters) → void: Available on BridgeModule, provided by the BridgeModuleFromJson extension
Create ports in the module based on the portInfo and parameters.
addStructMap(String structFieldFullName, PortReference reference) → void: Creates a mapping from structFieldFullName to a PortReference, so that each time port receives structFieldFullName, it will actually return the specified reference.
addStructMapsFromJson(Map<String, dynamic> structInfo) → void: Available on BridgeModule, provided by the BridgeModuleFromJson extension
Calls addStructMap for each entry in the structInfo map.
addSubModule<BridgeModuleType extends BridgeModule>(BridgeModuleType subModule) → BridgeModuleType: Adds a submodule to this module and establishes parent-child relationship.
addTypedInOut<LogicType extends Logic>(String name, LogicType source) → LogicType: Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
inherited
addTypedInput<LogicType extends Logic>(String name, LogicType source) → LogicType: Registers a signal as an input to this Module and returns an input port that can be consumed. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
inherited
addTypedOutput<LogicType extends Logic>(String name, LogicType logicGenerator({String name})) → LogicType: Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it. The type of the port will be LogicType and constructed via logicGenerator, which must properly update the name of the generated LogicType as well.
inherited
build() → Future<void>: Builds the Module and all subModules within it.
override
buildAndGenerateRTL({Logger? logger, String outputPath = 'output'}) → Future<void>: Calls build and generates SystemVerilog and a filelist into the outputPath, with optional logging sent to the logger.
createArrayPort(String portName, PortDirection direction, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → PortReference: Add array port with the given portName, direction, dimensions and elementWidth.
createParameter(String paramName, String value, {String type = 'int', bool isMapped = false, bool mergeIfExist = false}) → void: Creates a parameter definition with configurable instantiation mapping.
createPort(String portName, PortDirection direction, {int width = 1}) → PortReference: Creates a new port with the specified characteristics.
definitionVerilog(String definitionType) → String?: A custom SystemVerilog definition to be produced for this Module.
override
findSubModule(Pattern pattern) → Module?: Available on Module, provided by the RohdBridgeModuleExtensions extension
Searches for one sub-module matching pattern in the same way as findSubModules. If more than one module is found, an exception is thrown.
findSubModules(Pattern pattern) → Iterable<Module>: Available on Module, provided by the RohdBridgeModuleExtensions extension
Searches for sub-modules by instance name pattern within this Module. The String representation being matched against uses / as a separator for hierarchy.
generateSynth() → String: Returns a synthesized version of this Module.
inherited
getHierarchyDownTo(Module instance) → List<Module>?: Available on Module, provided by the RohdBridgeModuleExtensions extension
Returns a list of instances between calling module this and the provided instance, where the first element is this and the last element is instance.
hierarchy() → Iterable<Module>: Computes the same thing as Module.hierarchy after build, but can also be run before build with only context about ROHD Bridge-aware hierarchy.
override
hierarchyString([int indent = 0]) → String: Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
inOut(String name) → Logic: Accesses the Logic associated with this Modules inOut port named name.
inherited
inOutSource(String name) → Logic: The original source provided to the creation of the inOut port name via addInOut or addInOutArray.
inherited
input(String name) → Logic: Accesses the Logic associated with this Modules input port named name.
inherited
inputSource(String name) → Logic: The original source provided to the creation of the input port name via addInput or addInputArray.
inherited
instantiationVerilog(String instanceType, String instanceName, Map<String, String> ports) → String: Generates custom SystemVerilog to be injected in place of a module instantiation.
override
interface(String name) → InterfaceReference<PairInterface>: Gets a reference to an interface by name.
isInOut(Logic signal) → bool: Returns true iff signal is the same Logic as the inOut port of this Module with the same name.
inherited
isInput(Logic signal) → bool: Returns true iff signal is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic signal) → bool: Returns true iff signal is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic signal) → bool: Returns true iff signal is the same Logic as an input, output, or inOut port of this Module with the same name.
inherited
noSuchMethod(Invocation invocation) → dynamic: Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic: Accesses the Logic associated with this Modules output port named name.
inherited
overrideParameter(String paramName, String newValue) → void: Override the value of a parameter named paramName with newValue.
port(String portRefString) → PortReference: Creates a port reference from a string representation with advanced parsing.
pullUpInterface(InterfaceReference<PairInterface> subModuleIntf, {String? newIntfName, bool allowIntfUniquification = true, Set<String>? exceptPorts, String portUniquify(String logical, String physical)?}) → InterfaceReference<PairInterface>: Creates a hierarchical connection by pulling an interface up from a submodule.
pullUpParameter(BridgeModule srcInst, String srcParam, {String? newParamName}) → void: Pull up a passthrough parameter to this level
pullUpPort(PortReference subModulePort, {String? newPortName, bool allowPortUniquification = true}) → PortReference: Creates a hierarchical port connection by pulling a port up from a submodule.
renamePort(String currentName, String newName) → void: Creates a logical alias for an existing port without affecting RTL generation.
tieOffInterface(InterfaceReference<PairInterface> intfRef, dynamic value) → void: Tie off input ports of intfRef from to value.
toString() → String: A string representation of this object.
inherited
tryInOut(String name) → Logic?: Provides the inOut named name if it exists, otherwise null.
inherited
tryInput(String name) → Logic?: Provides the input named name if it exists, otherwise null.
inherited
tryOutput(String name) → Logic?: Provides the output named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool: The equality operator.
inherited

BridgeModule class

Constructors

Properties

Methods

Operators

rohd_bridge library