createParameter method
Creates a parameter definition with configurable instantiation mapping.
This method creates both a parameter definition (for module definition) and configures its instantiation behavior. The parameter can either be mapped to a parent parameter or tied to a static value.
The paramName
specifies the name of the parameter to create, value
provides the default value for the parameter, and type
sets the
SystemVerilog type. The isMapped
controls instantiation mapping
behavior: when true
, it maps to parent parameter
(.paramName(paramName)
), and when false
, it uses static value
(.paramName(value)
). The mergeIfExist
allows merging with existing
parameters of same name/value.
When mergeIfExist
is true
and a parameter with the same name and value
already exists, the method returns without creating a duplicate.
Throws an Exception if a parameter with the same name but different
value already exists and mergeIfExist
is false.
Implementation
void createParameter(String paramName, String value,
{String type = 'int', bool isMapped = false, bool mergeIfExist = false}) {
// TODO(mkorbel1): Is it appropriate for `isMapped` to be here? Maybe we
// should have more robust checking and separation between creation of a
// parameter and applying an instantiation parameter?
// check if a parameter with this name and value already exists
final existingDefinitionParameter =
definitionParameters.firstWhereOrNull((dp) => dp.name == paramName);
if (existingDefinitionParameter != null) {
final paramVal = existingDefinitionParameter.defaultValue;
if (paramVal == value && mergeIfExist) {
// if the parameter already exists at this level with same value
// merge the parameter mappings without creating
// additional parameters
return;
} else {
// its safer to throw RohdBridgeException in this case at this stage
// traditional tools do generate rtl with merged mappings but end up
// failing at rtl validation due to lint issues
throw RohdBridgeException(
'Parameter $paramName already exists at $name. Please use a '
'different name.');
}
}
// update default parameter
final newParam = SystemVerilogParameterDefinition(
paramName,
type: type,
defaultValue: value,
);
_definitionParameters.add(newParam);
// update instantiation parameters (only if not already overridden)
if (!instantiationParameters.containsKey(paramName)) {
_instantiationParameters[paramName] = isMapped ? paramName : value;
}
}