BridgeModule constructor

BridgeModule(
  1. String definitionName, {
  2. List<SystemVerilogParameterDefinition>? definitionParameters,
  3. Map<String, String>? instantiationParameters,
  4. String? name,
  5. bool reserveDefinitionName = true,
  6. bool reserveName = false,
  7. bool allowUniquification = true,
  8. bool isSystemVerilogLeaf = false,
})

Creates a new BridgeModule with enhanced connectivity capabilities.

The definitionName specifies the module name used in SystemVerilog generation. For external SystemVerilog modules, this should match the existing module name exactly.

The name is the instance name when instantiated of this module instance. If the instance name of this module is important to keep consistent, you should set reserveName to true so it will not change.

Reservation of names and definitionNames will cause an exception to be thrown during SystemVerilog generation if it is not possible to maintain the reserved name.

If isSystemVerilogLeaf is true, then this module is a leaf SystemVerilog module, meaning it is not generated by ROHD Bridge and should not generate a SystemVerilog definition. Also, it means reserveDefinitionName must be true to ensure that the definition name is reserved for the SystemVerilog module.

Implementation

BridgeModule(
  String definitionName, {
  List<SystemVerilogParameterDefinition>? definitionParameters,
  Map<String, String>? instantiationParameters,
  String? name,
  super.reserveDefinitionName = true,
  super.reserveName,
  this.allowUniquification = true,
  this.isSystemVerilogLeaf = false,
})  : _definitionParameters = List.of(definitionParameters ?? const []),
      _instantiationParameters = Map.of(instantiationParameters ?? const {}),
      super(
        definitionName: definitionName,
        name: name ?? definitionName,
      ) {
  if (isSystemVerilogLeaf && !reserveDefinitionName) {
    throw RohdBridgeException(
        'If isSystemVerilogLeaf is true, then reserveDefinitionName must'
        ' also be true.');
  }
}