buildAndGenerateRTL method
Calls build and generates SystemVerilog and a filelist into the
outputPath
, with optional logging sent to the logger
.
Implementation
Future<void> buildAndGenerateRTL(
{Logger? logger, String outputPath = 'output'}) async {
var synthResults = <SynthesisResult>{};
// Build
try {
await build();
final synthBuilder = SynthBuilder(this, SystemVerilogSynthesizer());
synthResults = synthBuilder.synthesisResults;
final defNames =
synthResults.map((result) => result.module.definitionName);
logger
?..info('Build Complete...\n')
..info('Found ${synthResults.length} hierarchical instances in '
'design $name')
..info('Synth Results: ${defNames.join(', ')}');
} on Exception catch (e, stackTrace) {
logger != null
? logger.error('Build failed $e, $stackTrace')
: throw RohdBridgeException('Build failed $e, $stackTrace');
}
// Write out RTL
final outputGenerationPath = '$outputPath/rtl';
Directory(outputGenerationPath).createSync(recursive: true);
final filelistContents = StringBuffer();
logger?.sectionSeparator('Generating RTL');
final fileIoFutures = <Future<void>>[];
for (final synthResult in synthResults) {
final fileName = '${synthResult.module.definitionName}.sv';
final filePath = '$outputGenerationPath/$fileName';
filelistContents.writeln('./rtl/$fileName');
fileIoFutures.add(File(filePath)
.writeAsString(synthResult.toSynthFileContents().join('\n')));
logger?.finer('Generated file ${Directory(filePath).absolute.path}');
}
await Future.wait(fileIoFutures);
File('$outputPath/filelist.f')
.writeAsStringSync(filelistContents.toString());
logger?.fine('done!');
}