5. Memory Access

5.1. Access Alignment

For all memory operations, memory access address must be aligned to the bitwidth of .type. In cases where the bitwidth of .type is smaller than 32b, the address must be aligned to the accessed size, defined as the product of the bitwidth and the vector element count.

Examples of Memory Access Alignment Requirements

Instruction	Address Alignment
ld.64b	64
ld.v2.64b	64
ld.8b	8
ld.v2.8b	16

5.2. Data Size

Maximum data size is determined by memory access type, operand’s bitwidth and element count.

Supported data sizes for memory instructions

Number of elements	Bitwidth
single element	.8b, .16b, .32b, .64b
.v2	.8b, .16b, .32b, .64b
.v3	.32b
.v4	.8b, .16b, .32b, .64b
.v8	.32b

Instruction definitions may provide additional restrictions on the supported data sizes.

5.3. Cache Control

Memory instructions support optional cache control qualifiers that serve as performance hints to the cache subsystem. These qualifiers are advisory and may not be honored by the system; they have no effect on the memory consistency behavior of the program.

Cache control definitions for atomic instructions

Cache control	Description
.uc	Do not cache the data in any cache level.
.L2wb	Write data to L2 but not the next level cache.
.L3wb	Write data to L3 but not the next level cache.

Cache controls for non-atomic instructions are described in their respective instruction definitions.