Comparison and Selection

5. Comparison and Selection#

5.1. scmp#

Compare two signed integer values.

predicate destination:

scmp.cop.type  pred, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .16b, .32b, .64b }


  - pred is a predicate register
  - src0, src1 can be registers or immediates

  * src0, src1 are interpreted as signed integers.

Restrictions

  • bitwidth of src0 and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

register destination:

scmp.cop.type  dst, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .16b, .32b, .64b }


  - dst is a 32-bit register
  - src0, src1 can be registers or immediates

  * src0, src1 are interpreted as signed integers.

Restrictions

  • bitwidth of src0 and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Semantics:

register destination#
dst[31:0] = (src0 .cop src1) ? ~0 : 0
predicate destination#
pred = (src0 .cop src1) ? 1 : 0

Notes:

  • scmp.eq is functionally equivalent to ucmp.eq.

  • scmp.ne is functionally equivalent to ucmp.ne.

Examples:

.reg .16b %src0_16b, %src1_16b;
.reg .32b %dst, %src0, %src1, %src2;
.pred %pin, %pout;

// signed comparison of 32-bit elements (predicate result)
scmp.eq.32b  %pout, %src0, %src1;
// signed comparison of 32-bit elements (register result)
scmp.eq.32b  %dst, %src0, %src1;
// signed comparison of 16-bit elements (register result: %dst contains either 0xFFFFFFFF or 0x00000000)
scmp.ge.16b  %dst, %src0_16b, %src1_16b;

5.2. ucmp#

Compare two unsigned integer values.

Unsigned comparison with predicate destination:

ucmp.cop.type   pred, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .16b, .32b, .64b }


  - pred is a predicate register
  - src0, src1 can be registers or immediates

  * src0, src1 are interpreted as unsigned integers.

Restrictions

  • bitwidth of src0 and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Unsigned comparison with register destination:

ucmp.cop.type   dst, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .16b, .32b, .64b }


  - dst is a 32-bit register
  - src0, src1 can be registers or immediates

  * src0, src1 are interpreted as unsigned integers.

Restrictions

  • bitwidth of src0 and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

packed:

ucmp.cop.type   dst, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .16bx2 }


  - dst, src0, src1 are 2x16-bit vector registers

  * src0, src1 are interpreted as unsigned integers.

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Semantics:

.type == .16bx2#
dst[15:0] = (src0[15:0] .cop src1[15:0]) ? ~0 : 0
dst[31:16] = (src0[31:16] .cop src1[31:16]) ? ~0 : 0
register destination#
dst[31:0] = (src0 .cop src1) ? ~0 : 0
predicate destination#
pred = (src0 .cop src1) ? 1 : 0

Notes:

  • ucmp.eq is functionally equivalent to scmp.eq.

  • ucmp.ne is functionally equivalent to scmp.ne.

Examples:

.reg .16b %src0_16b, %src1_16b;
.reg .32b %dst, %src0, %src1, %src2;
.pred %pin, %pout;

// unsigned comparison of 32-bit elements (predicate result)
ucmp.eq.32b  %pout, %src0, %src1;
// unsigned comparison of 32-bit elements (register result)
ucmp.eq.32b  %dst, %src0, %src1;
// unsigned comparison of 16-bit elements (register result: %dst contains either 0xFFFFFFFF or 0x00000000)
ucmp.ge.16b  %dst, %src0_16b, %src1_16b;
// element-wise unsigned comparison of 2x16-bit packed values (dst is bitmask, src operands are .v2.16b)
.reg .v2.16b %pdst, %psrc0, %psrc1;
ucmp.le.16bx2  %pdst, %psrc0, %psrc1;

5.3. fcmp#

Compare two floating-point values.

Floating-point comparison with predicate destination:

fcmp.cop<.ftz>.type   pred, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .bf, .hf, .f, .df }


  - pred is a predicate register
  - src0, src1 can be registers or immediates

Restrictions

  • bitwidth of src0 and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Floating-point comparison with register destination:

fcmp.cop<.ftz>.type   dst, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .bf, .hf, .f, .df }


  - dst is a 32-bit register
  - src0, src1 can be registers or immediates

Restrictions

  • bitwidth of src0 and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

packed:

fcmp.cop<.ftz>.type   dst, src0, src1

  .cop = { .eq, .ne, .gt, .ge, .lt, .le }
  .type = { .bfx2, .hfx2 }


  - dst, src0, src1 are 2x16-bit vector registers

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#
dst[15:0] = (src0[15:0] .cop src1[15:0]) ? ~0 : 0
dst[31:16] = (src0[31:16] .cop src1[31:16]) ? ~0 : 0
register destination#
dst[31:0] = (src0 .cop src1) ? ~0 : 0
predicate destination#
pred = (src0 .cop src1) ? 1 : 0

Examples:

.reg .16b %src0_16b, %src1_16b;
.reg .32b %dst, %src0, %src1, %src2;
.pred %pin, %pout;

// comparison of single-precision elements (predicate result)
fcmp.eq.f  %pout, %src0, %src1;
// comparison of single-precision elements (register result)
fcmp.eq.f  %dst, %src0, %src1;
// comparison of half-precision elements (register result: %dst contains either 0xFFFFFFFF or 0x00000000)
fcmp.ge.hf  %dst, %src0_16b, %src1_16b;
// element-wise comparison of 2 x half-float packed values
// src operands are .v2.16b packed FP; dst is an integer bitmask (0xFFFF or 0x0000 per lane)
.reg .v2.16b %pdst, %psrc0, %psrc1;
fcmp.le.hfx2  %pdst, %psrc0, %psrc1;

5.4. sel#

Select one of two sources based on value.

Select based on register value:

sel.type   dst, src0, src1, src2

  .type = { .16b, .32b, .64b }


  - dst, src2 are registers
  - src0, src1 can be registers or immediates

Restrictions

  • bitwidth of dst, src0, src1, and src2 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Select based on predicate:

sel.type   dst, src0, src1, <!>pred

  .type = { .16b, .32b, .64b }


  - dst is a register
  - src0, src1 can be registers or immediates
  - pred is a predicate register

Restrictions

  • bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

  • introduced in PISA version 0.1

  • requires PISA target 100 or compatible

Semantics:

register selector#
dst = (src2 != 0) ? src0 : src1
predicate selector#
if ('!' is set)
   dst = (!pred == 1) ? src0 : src1
else
   dst = (pred == 1) ? src0 : src1

Notes:

The register-selector form performs a bitwise integer test on src2. For IEEE 754-compliant floating-point zero-checking, use fcmp.ne to produce a predicate and select using the predicate-selector form instead.

Examples:

.reg .32b %dst, %src0, %src1, %src2;
.pred %pin;

// select one of 32-bit elements (register selector)
sel.32b  %dst, %src0, %src1, %src2;
// select one of 32-bit elements (predicate selector)
sel.32b  %dst, %src0, %src1, %pin;
// select one of 32-bit elements (inverted predicate)
sel.32b  %dst, %src0, %src1, !%pin;
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