2. Floating Point#

2.1. `fabs`#

Compute the absolute value of a floating-point number.

Syntax:

fabs<.ftz>.type dst, src0

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fabs<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = |src0[15:0]|
dst[31:16] = |src0[31:16]|

default#

dst = |src0|

Notes:

If the source is NaN, then a quiet NaN is returned with its sign bit cleared.

Examples:

.reg .32b %dst, %src0;

// absolute value of a single-precision element
fabs.f  %dst, %src0;
// absolute value of a single-precision element with flush-to-zero
fabs.ftz.f  %dst, %src0;
// element-wise absolute value of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
fabs.hfx2  %dst_packed, %src0_packed;

2.2. `fadd`#

Add two floating-point numbers.

Syntax:

fadd<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fadd<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bfx2, .hfx2 }


  - dst, src0, src1 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = src0[15:0] + src1[15:0]
dst[31:16] = src0[31:16] + src1[31:16]

default#

dst = src0 + src1

Notes:

Enabling saturation via .dsat qualifier clamps the final result to [0.0, 1.0]. NaN results are flushed to +0.0.

Examples:

.reg .32b %dst, %src0, %src1;

// addition of single-precision elements
fadd.f  %dst, %src0, %src1;
// addition of single-precision elements with rounding
fadd.ru.f  %dst, %src0, %src1;
// element-wise addition of 2 x half-precision packed values
.reg .v2.16b %dst_packed, %src0_packed, %src1_packed;
fadd.hfx2  %dst_packed, %src0_packed, %src1_packed;

2.3. `fcos`#

Compute the cosine of a floating-point number.

Syntax:

fcos<.ftz>.type dst, src0

  .type = { .bf, .hf, .f }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fcos<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = cos(src0[15:0])
dst[31:16] = cos(src0[31:16])

default#

dst = cos(src0)

Notes:

The maximum relative error for fcos is 2 ULP.

Examples:

.reg .32b %dst, %src0;

// cosine value of a single-precision element
fcos.f  %dst, %src0;
// cosine value of a single-precision element with flush-to-zero
fcos.ftz.f  %dst, %src0;
// element-wise cosine of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
fcos.hfx2  %dst_packed, %src0_packed;

2.4. `fdiv`#

Divide two floating-point numbers.

Floating-point division:

fdiv<.rndmode><.ftz>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Fast floating-point division:

fdiv<.ftz>.fast.type dst, src0, src1

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

dst = src0 / src1

Notes:

The maximum relative error for fdiv with .fast qualifier is:

0.5 ULP for .bf, .hf
2.5 ULP for .f
2.0 ULP for .df

Instructions without .fast qualifier produce IEEE compliant result.

Examples:

.reg .32b %dst, %src0, %src1;

// division of single-precision elements
fdiv.f  %dst, %src0, %src1;
// division of single-precision elements with flush-to-zero
fdiv.ftz.f  %dst, %src0, %src1;
// fast division of single-precision elements
fdiv.fast.f  %dst, %src0, %src1;

2.5. `fexp2`#

Compute the base-2 exponential of a floating-point number.

Syntax:

fexp2<.ftz>.type dst, src0

  .type = { .bf, .hf, .f }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fexp2<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = 2^(src0[15:0])
dst[31:16] = 2^(src0[31:16])

default#

dst = 2^(src0)

Notes:

The maximum relative error for fexp2 is 2 ULP.

Examples:

.reg .32b %dst, %src0;

// base-2 exponential value of a single-precision element
fexp2.f  %dst, %src0;
// base-2 exponential value of a single-precision element with flush-to-zero
fexp2.ftz.f  %dst, %src0;
// element-wise base-2 exponential of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
fexp2.hfx2  %dst_packed, %src0_packed;

2.6. `flog2`#

Compute the base-2 logarithm of a floating-point number.

Syntax:

flog2<.ftz>.type dst, src0

  .type = { .bf, .hf, .f }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

flog2<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = log2(src0[15:0])
dst[31:16] = log2(src0[31:16])

default#

dst = log2(src0)

Notes:

The maximum relative error for flog2 is:

2^-23 for src0 value in the range of [0.5..1.5)
1 ULP for all other values

Examples:

.reg .32b %dst, %src0;

// base-2 log value of a single-precision element
flog2.f  %dst, %src0;
// base-2 log value of a single-precision element with flush-to-zero
flog2.ftz.f  %dst, %src0;
// element-wise base-2 log of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
flog2.hfx2  %dst_packed, %src0_packed;

2.7. `fmad`#

Compute the fused multiply-add of floating-point numbers.

Syntax:

fmad<.rndmode><.ftz><.dsat>.type dst, src0, src1, src2

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1, src2 can be registers or immediates

Restrictions

bitwidth of dst, src0, src1, and src2 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fmad<.rndmode><.ftz><.dsat>.type dst, src0, src1, src2

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bfx2, .hfx2 }


  - dst, src0, src1, src2 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = src0[15:0] * src1[15:0] + src2[15:0]
dst[31:16] = src0[31:16] * src1[31:16] + src2[31:16]

default#

dst = src0 * src1 + src2

Notes:

Enabling saturation via .dsat qualifier clamps the final result to [0.0, 1.0]. NaN results are flushed to +0.0.

Examples:

.reg .32b %dst, %src0, %src1, %src2;

// fused multiply-add of single-precision elements
fmad.f  %dst, %src0, %src1, %src2;
// fused multiply-add of single-precision elements with rounding
fmad.ru.f  %dst, %src0, %src1, %src2;
// element-wise fused multiply-add of 2 x half-precision packed values
.reg .v2.16b %dst_packed, %src0_packed, %src1_packed, %src2_packed;
fmad.hfx2  %dst_packed, %src0_packed, %src1_packed, %src2_packed;

2.8. `fmax`#

Find the maximum of two floating-point numbers.

Syntax:

fmax<.ftz><.dsat><.nanp>.type dst, src0, src1

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fmax<.ftz><.dsat><.nanp>.type dst, src0, src1

  .type = { .bfx2, .hfx2 }


  - dst, src0, src1 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = fmax(src0[15:0], src1[15:0])
dst[31:16] = fmax(src0[31:16], src1[31:16])

default#

dst = fmax(src0, src1)

Notes:

By default, NaN inputs follow the IEEE 754 maximumNumber semantics: if one of the sources is NaN, the other source is returned, and if both sources are NaN a quiet NaN is returned.

When .nanp is specified, NaN inputs follow the IEEE 754 maximum semantics: if either source is a NaN of any type, the result is a quiet NaN.

Enabling saturation via .dsat qualifier clamps the final result to [0.0, 1.0]. NaN results are flushed to +0.0.

Examples:

.reg .32b %dst, %src0, %src1;

// maximum value of a single-precision element
fmax.f  %dst, %src0, %src1;
// maximum value of a single-precision element with flush-to-zero
fmax.ftz.f  %dst, %src0, %src1;
// maximum value of a single-precision element with NaN propagation
fmax.nanp.f  %dst, %src0, %src1;
// element-wise maximum of 2 x half-float packed values
.reg .v2.16b %dst_packed, %src0_packed, %src1_packed;
fmax.hfx2  %dst_packed, %src0_packed, %src1_packed;

2.9. `fmin`#

Find the minimum of two floating-point numbers.

Syntax:

fmin<.ftz><.dsat><.nanp>.type dst, src0, src1

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fmin<.ftz><.dsat><.nanp>.type dst, src0, src1

  .type = { .bfx2, .hfx2 }


  - dst, src0, src1 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = fmin(src0[15:0], src1[15:0])
dst[31:16] = fmin(src0[31:16], src1[31:16])

default#

dst = fmin(src0, src1)

Notes:

By default, NaN inputs follow the IEEE 754 minimumNumber semantics: if one of the sources is NaN, the other source is returned, and if both sources are NaN a quiet NaN is returned.

When .nanp is specified, NaN inputs follow the IEEE 754 minimum semantics: if either source is a NaN of any type, the result is a quiet NaN.

Enabling saturation via .dsat qualifier clamps the final result to [0.0, 1.0]. NaN results are flushed to +0.0.

Examples:

.reg .32b %dst, %src0, %src1;

// minimum value of a single-precision element
fmin.f  %dst, %src0, %src1;
// minimum value of a single-precision element with flush-to-zero
fmin.ftz.f  %dst, %src0, %src1;
// minimum value of a single-precision element with NaN propagation
fmin.nanp.f  %dst, %src0, %src1;
// element-wise minimum of 2 x half-float packed values
.reg .v2.16b %dst_packed, %src0_packed, %src1_packed;
fmin.hfx2  %dst_packed, %src0_packed, %src1_packed;

2.10. `fmul`#

Multiply two floating-point numbers.

Widening floating-point multiply:

fmul.precision<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .precision = { .full }
  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bf, .hf }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of src0 and src1 must match the bitwidth of .type
bitwidth of dst must be twice the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Floating-point multiply:

fmul<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fmul<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bfx2, .hfx2 }


  - dst, src0, src1 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.precision == .full#

src0_extend = extend(src0, bitwidth(.type)*2)
src1_extend = extend(src1, bitwidth(.type)*2)
dst = src0_extend * src1_extend

.type == .bfx2 || .type == .hfx2#

dst[15:0] = src0[15:0] * src1[15:0]
dst[31:16] = src0[31:16] * src1[31:16]

default#

dst = src0 * src1

Notes:

Enabling saturation via .dsat qualifier clamps the final result to [0.0, 1.0]. NaN results are flushed to +0.0.

Examples:

.reg .16b %srch0, %srch1;
.reg .32b %dst, %src0, %src1;

// multiplication of single-precision elements
fmul.f  %dst, %src0, %src1;
// multiplication of single-precision elements with rounding
fmul.ru.f  %dst, %src0, %src1;
// element-wise multiplication of 2 x half-precision packed values
.reg .v2.16b %dst_packed, %src0_packed, %src1_packed;
fmul.hfx2  %dst_packed, %src0_packed, %src1_packed;
// multiplication of half-precision elements with full precision
fmul.full.hf  %dst, %srch0, %srch1;

2.11. `fneg`#

Negate a floating-point number.

Syntax:

fneg<.ftz>.type dst, src0

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fneg<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = -src0[15:0]
dst[31:16] = -src0[31:16]

default#

dst = -src0

Examples:

.reg .32b %dst, %src0;

// negate value of a single-precision element
fneg.f  %dst, %src0;
// negate value of a single-precision element with flush-to-zero
fneg.ftz.f  %dst, %src0;
// element-wise negate of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
fneg.hfx2  %dst_packed, %src0_packed;

2.12. `frc`#

Compute the fractional part of a floating-point number.

Syntax:

frc<.ftz>.type dst, src0

  .type = { .f }


  - dst is a 32-bit register
  - src0 can be a 32-bit register or an immediate

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

dst = src0 - round(src0, .rd)

Notes:

The .rd rounding mode is always applied for fraction.

Examples:

.reg .32b %dst, %src0;

// fraction value of a single-precision element
frc.f  %dst, %src0;
// fraction value of a single-precision element with flush-to-zero
frc.ftz.f  %dst, %src0;

2.13. `frcp`#

Compute the reciprocal of a floating-point number.

Syntax:

frcp<.ftz>.type dst, src0

  .type = { .bf, .hf, .f }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

frcp<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = 1/src0[15:0]
dst[31:16] = 1/src0[31:16]

default#

dst = 1/src0

Notes:

The maximum relative error for frcp is 1 ULP.

Examples:

.reg .32b %dst, %src0;

// reciprocal value of a single-precision element
frcp.f  %dst, %src0;
// reciprocal value of a single-precision element with flush-to-zero
frcp.ftz.f  %dst, %src0;
// element-wise reciprocal of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
frcp.hfx2  %dst_packed, %src0_packed;

2.14. `frsqrt`#

Compute the reciprocal square root of a floating-point number.

Syntax:

frsqrt<.ftz>.fast.type dst, src0

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

frsqrt<.ftz>.fast.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = 1/sqrt(src0[15:0])
dst[31:16] = 1/sqrt(src0[31:16])

default#

dst = 1/sqrt(src0)

Notes:

The maximum relative error for frsqrt is 1 ULP.

Examples:

.reg .32b %dst, %src0;

// reciprocal square root value of a single-precision element
frsqrt.fast.f  %dst, %src0;
// reciprocal square root value of a single-precision element with flush-to-zero
frsqrt.ftz.fast.f  %dst, %src0;
// element-wise reciprocal square root of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
frsqrt.fast.hfx2  %dst_packed, %src0_packed;

2.15. `fsin`#

Compute the sine of a floating-point number.

Syntax:

fsin<.ftz>.type dst, src0

  .type = { .bf, .hf, .f }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fsin<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = sin(src0[15:0])
dst[31:16] = sin(src0[31:16])

default#

dst = sin(src0)

Notes:

The maximum relative error for fsin is 2 ULP.

Examples:

.reg .32b %dst, %src0;

// sine value of a single-precision element
fsin.f  %dst, %src0;
// sine value of a single-precision element with flush-to-zero
fsin.ftz.f  %dst, %src0;
// element-wise sine of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
fsin.hfx2  %dst_packed, %src0_packed;

2.16. `fsqrt`#

Compute the square root of a floating-point number.

Floating-point square root:

fsqrt<.rndmode><.ftz>.type dst, src0

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .f, .df }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Fast floating-point square root:

fsqrt<.ftz>.fast.type dst, src0

  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fsqrt<.ftz>.fast.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = sqrt(src0[15:0])
dst[31:16] = sqrt(src0[31:16])

default#

dst = sqrt(src0)

Notes:

Instructions with .fast qualifier result in the maximum relative error of:

2 ULP for .df
1 ULP for all other .type values

Instructions without .fast qualifier produce IEEE compliant result.

Examples:

.reg .32b %dst, %src0;

// square root value of a single-precision element
fsqrt.f  %dst, %src0;
// square root value of a single-precision element with flush-to-zero
fsqrt.ftz.f  %dst, %src0;
// element-wise square root of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
fsqrt.fast.hfx2  %dst_packed, %src0_packed;

2.17. `fsub`#

Subtract two floating-point numbers.

Syntax:

fsub<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bf, .hf, .f, .df }


  - dst is a register
  - src0, src1 can be registers or immediates

Restrictions

bitwidth of dst, src0, and src1 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

fsub<.rndmode><.ftz><.dsat>.type dst, src0, src1

  .rndmode = { .re, .rd, .ru, .rz, .rna }
  .type = { .bfx2, .hfx2 }


  - dst, src0, src1 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = src0[15:0] - src1[15:0]
dst[31:16] = src0[31:16] - src1[31:16]

default#

dst = src0 - src1

Notes:

Enabling saturation via .dsat qualifier clamps the final result to [0.0, 1.0]. NaN results are flushed to +0.0.

Examples:

.reg .32b %dst, %src0, %src1;

// subtraction of single-precision elements
fsub.f  %dst, %src0, %src1;
// subtraction of single-precision elements with rounding
fsub.ru.f  %dst, %src0, %src1;
// element-wise subtraction of 2 x half-precision packed values
.reg .v2.16b %dst_packed, %src0_packed, %src1_packed;
fsub.hfx2  %dst_packed, %src0_packed, %src1_packed;

2.18. `ftanh`#

Compute the hyperbolic tangent of a floating-point number.

Syntax:

ftanh<.ftz>.type dst, src0

  .type = { .bf, .hf, .f }


  - dst is a register
  - src0 can be a register or an immediate

Restrictions

bitwidth of dst and src0 must match the bitwidth of .type

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

packed:

ftanh<.ftz>.type dst, src0

  .type = { .bfx2, .hfx2 }


  - dst, src0 are 2x16-bit vector registers

PISA Notes

introduced in PISA version 0.1
requires PISA target 100 or compatible

Semantics:

.type == .bfx2 || .type == .hfx2#

dst[15:0] = tanh(src0[15:0])
dst[31:16] = tanh(src0[31:16])

default#

dst = tanh(src0)

Notes:

The maximum relative error for ftanh is 2 ULP.

Examples:

.reg .32b %dst, %src0;

// hyperbolic tangent value of a single-precision element
ftanh.f  %dst, %src0;
// hyperbolic tangent value of a single-precision element with flush-to-zero
ftanh.ftz.f  %dst, %src0;
// element-wise hyperbolic tangent of a 2 x half-float packed value
.reg .v2.16b %dst_packed, %src0_packed;
ftanh.hfx2  %dst_packed, %src0_packed;

Floating Point

Contents

2. Floating Point#

2.1. fabs#

2.2. fadd#

2.3. fcos#

2.4. fdiv#

2.5. fexp2#

2.6. flog2#

2.7. fmad#

2.8. fmax#

2.9. fmin#

2.10. fmul#

2.11. fneg#

2.12. frc#

2.13. frcp#

2.14. frsqrt#

2.15. fsin#

2.16. fsqrt#

2.17. fsub#

2.18. ftanh#

2.1. `fabs`#

2.2. `fadd`#

2.3. `fcos`#

2.4. `fdiv`#

2.5. `fexp2`#

2.6. `flog2`#

2.7. `fmad`#

2.8. `fmax`#

2.9. `fmin`#

2.10. `fmul`#

2.11. `fneg`#

2.12. `frc`#

2.13. `frcp`#

2.14. `frsqrt`#

2.15. `fsin`#

2.16. `fsqrt`#

2.17. `fsub`#

2.18. `ftanh`#