3. Floating Point Support

3.1. Data Types

PISA virtual machine supports floating point data types of multiple precisions.

Floating Point Data Types

Name	Bit size	Sign bit	Exp bits	Mantissa bits	IEEE-754 compliance
Single precision (.f)	32	[31:31]	[30:23]	[22:0]	Y - IEEE-754-1985
Double precision (.df)	64	[63:63]	[62:52]	[51:0]	Y - IEEE-754-1985
Half float (.hf)	16	[15:15]	[14:10]	[9:0]	Y - IEEE-754-2008
Bfloat16 (.bf)	16	[15:15]	[14:7]	[6:0]	N

3.2. Rounding Mode

Rounding mode determines how the result of a floating-point operation is rounded when it cannot be represented exactly in the destination type. It is specified on a per-instruction basis using the rounding mode qualifier.

Floating Point Rounding Modes

Qualifier	Description
.re	Round to nearest even.
.rd	Round down, toward minus infinity.
.ru	Round up, toward plus infinity.
.rz	Round toward zero.
.rna	Round to nearest, ties away from zero.

Note

Default rounding mode for all floating-point operations is .re.

3.3. Flush-To-Zero (FTZ)

By default PISA floating-point arithmetic instructions retain denormal values. A floating-point instruction may opt to flush its denormal sources and result (post rounding) to sign-preserving zero by specifying the .ftz qualifier.

3.4. Not A Number (NaN)

An IEEE-754 NaN has an exponent field with all bits set and a nonzero fraction field. A signaling NaN (sNaN) has zero as the Most-Significant Bit (MSB) of its fraction field, while a quiet NaN (qNaN) has one as the MSB of its fraction field.

When a qNaN is an input to a floating point instruction, the same qNaN is returned as output. If there are multiple NaN input values, one of them will be selected as the output NaN value.

3.5. Destination Saturation (DSat)

Floating-point instructions may support an optional destination saturation via .dsat qualifier. When .dsat is specified, the result of the instruction is clamped to the specific range or value. Exact behavior of this qualifier is specified in the instruction description.