DPC++ Runtime
Runtime libraries for oneAPI DPC++
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common.hpp File Reference
#include <sycl/ext/intel/esimd/detail/defines_elementary.hpp>
#include <sycl/ext/intel/esimd/native/common.hpp>
#include <sycl/ext/intel/esimd/xmx/common.hpp>
#include <cstdint>
#include <type_traits>
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Classes

struct  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_expand_type< T >
 
struct  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_bitcast_type< T >
 
class  sycl::_V1::ext::intel::experimental::esimd::detail::cache_hint_wrap< Hint >
 

Namespaces

 sycl
 ---— Error handling, matching OpenCL plugin semantics.
 
 sycl::_V1
 
 sycl::_V1::ext
 
 sycl::_V1::ext::intel
 
 sycl::_V1::ext::intel::experimental
 
 sycl::_V1::ext::intel::experimental::esimd
 
 sycl::_V1::ext::intel::experimental::esimd::detail
 

Enumerations

enum  sycl::_V1::ext::intel::experimental::esimd::lsc_scope : uint8_t {
  sycl::_V1::ext::intel::experimental::esimd::lsc_scope::group = 0, sycl::_V1::ext::intel::experimental::esimd::lsc_scope::local = 1, sycl::_V1::ext::intel::experimental::esimd::lsc_scope::tile = 2, sycl::_V1::ext::intel::experimental::esimd::lsc_scope::gpu = 3,
  sycl::_V1::ext::intel::experimental::esimd::lsc_scope::gpus = 4, sycl::_V1::ext::intel::experimental::esimd::lsc_scope::system = 5, sycl::_V1::ext::intel::experimental::esimd::lsc_scope::sysacq = 6
}
 The scope that lsc_fence operation should apply to Supported platforms: DG2, PVC. More...
 
enum  sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op : uint8_t {
  sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op::none = 0, sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op::evict = 1, sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op::invalidate = 2, sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op::discard = 3,
  sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op::clean = 4, sycl::_V1::ext::intel::experimental::esimd::lsc_fence_op::flushl3 = 5
}
 The lsc_fence operation to apply to caches Supported platforms: DG2, PVC. More...
 
enum  sycl::_V1::ext::intel::experimental::esimd::lsc_memory_kind : uint8_t { sycl::_V1::ext::intel::experimental::esimd::lsc_memory_kind::untyped_global = 0, sycl::_V1::ext::intel::experimental::esimd::lsc_memory_kind::untyped_global_low_pri = 1, sycl::_V1::ext::intel::experimental::esimd::lsc_memory_kind::typed_global = 2, sycl::_V1::ext::intel::experimental::esimd::lsc_memory_kind::shared_local = 3 }
 The specific LSC shared function to fence with lsc_fence Supported platforms: DG2, PVC. More...
 
enum  sycl::_V1::ext::intel::experimental::esimd::lsc_data_size : uint8_t {
  sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::default_size = 0, sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u8 = 1, sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u16 = 2, sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u32 = 3,
  sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u64 = 4, sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u8u32 = 5, sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u16u32 = 6, sycl::_V1::ext::intel::experimental::esimd::lsc_data_size::u16u32h = 7
}
 Data size or format to read or store. More...
 
enum  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size : uint8_t {
  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n1 = 1, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n2 = 2, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n3 = 3, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n4 = 4,
  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n8 = 5, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n16 = 6, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n32 = 7, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_vector_size::n64 = 8
}
 
enum  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_data_order : uint8_t { sycl::_V1::ext::intel::experimental::esimd::detail::lsc_data_order::nontranspose = 1, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_data_order::transpose = 2 }
 
enum  sycl::_V1::ext::intel::experimental::esimd::cache_hint : uint8_t {
  sycl::_V1::ext::intel::experimental::esimd::cache_hint::none = 0, sycl::_V1::ext::intel::experimental::esimd::cache_hint::uncached = 1, sycl::_V1::ext::intel::experimental::esimd::cache_hint::cached = 2, sycl::_V1::ext::intel::experimental::esimd::cache_hint::write_back = 3,
  sycl::_V1::ext::intel::experimental::esimd::cache_hint::write_through = 4, sycl::_V1::ext::intel::experimental::esimd::cache_hint::streaming = 5, sycl::_V1::ext::intel::experimental::esimd::cache_hint::read_invalidate = 6
}
 L1 or L3 cache hint kinds. More...
 
enum  sycl::_V1::ext::intel::experimental::esimd::detail::lsc_action { sycl::_V1::ext::intel::experimental::esimd::detail::lsc_action::prefetch, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_action::load, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_action::store, sycl::_V1::ext::intel::experimental::esimd::detail::lsc_action::atomic }
 
enum  sycl::_V1::ext::intel::experimental::esimd::split_barrier_action : uint8_t { sycl::_V1::ext::intel::experimental::esimd::split_barrier_action::wait = 0, sycl::_V1::ext::intel::experimental::esimd::split_barrier_action::signal = 1 }
 Represents a split barrier action. More...
 

Functions

template<lsc_vector_size VS>
constexpr void sycl::_V1::ext::intel::experimental::esimd::detail::check_lsc_vector_size ()
 
template<typename T , lsc_data_size DS>
constexpr void sycl::_V1::ext::intel::experimental::esimd::detail::check_lsc_data_size ()
 
template<lsc_vector_size VS>
constexpr uint8_t sycl::_V1::ext::intel::experimental::esimd::detail::to_int ()
 
template<int VS>
constexpr lsc_vector_size sycl::_V1::ext::intel::experimental::esimd::detail::to_lsc_vector_size ()
 
template<typename T , lsc_data_size DS>
constexpr lsc_data_size sycl::_V1::ext::intel::experimental::esimd::detail::finalize_data_size ()
 
constexpr lsc_data_size sycl::_V1::ext::intel::experimental::esimd::detail::expand_data_size (lsc_data_size DS)
 
constexpr bool sycl::_V1::ext::intel::experimental::esimd::detail::are_both (cache_hint First, cache_hint Second, cache_hint Val)
 
template<lsc_action Action, cache_hint L1, cache_hint L3>
constexpr void sycl::_V1::ext::intel::experimental::esimd::detail::check_lsc_cache_hint ()