DPC++ Runtime
Runtime libraries for oneAPI DPC++
common.hpp
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//==-------------- native/memory.hpp - DPC++ Explicit SIMD API -------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Explicit SIMD API types used in native ESIMD APIs.
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//===----------------------------------------------------------------------===//
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#pragma once
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#include <
sycl/detail/defines_elementary.hpp
>
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#include <cstdint>
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namespace
sycl
{
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inline
namespace
_V1 {
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namespace
ext::intel::esimd::native::lsc {
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// TODO move all LSC-related "common" APIs here
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enum class
atomic_op
: uint8_t {
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inc
= 0x08,
// atomic integer increment
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dec
= 0x09,
// atomic integer decrement
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load
= 0x0a,
// atomic load
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store
= 0x0b,
// atomic store
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add
= 0x0c,
// atomic integer add
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sub
= 0x0d,
// atomic integer subtract
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smin
= 0x0e,
// atomic signed int min
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smax
= 0x0f,
// atomic signed int max
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umin
= 0x10,
// atomic unsigned int min
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umax
= 0x11,
// atomic unsigned int max
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cmpxchg
= 0x12,
// atomic int compare and swap
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fadd
= 0x13,
// floating-point add
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fsub
= 0x14,
// floating-point subtract
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fmin
= 0x15,
// floating-point min
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fmax
= 0x16,
// floating-point max
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fcmpxchg
= 0x17,
// floating-point CAS
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bit_and
= 0x18,
// logical (bitwise) AND
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bit_or
= 0x19,
// logical (bitwise) OR
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bit_xor
= 0x1a,
// logical (bitwise) XOR
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};
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}
// namespace ext::intel::esimd::native::lsc
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}
// namespace _V1
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}
// namespace sycl
defines_elementary.hpp
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op
atomic_op
LSC atomic operation codes.
Definition:
common.hpp:39
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::umin
@ umin
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fsub
@ fsub
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::dec
@ dec
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::add
@ add
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::smin
@ smin
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::cmpxchg
@ cmpxchg
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fmax
@ fmax
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fadd
@ fadd
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::umax
@ umax
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::sub
@ sub
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::store
@ store
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fmin
@ fmin
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::smax
@ smax
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::inc
@ inc
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fcmpxchg
@ fcmpxchg
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::load
@ load
sycl::_V1::bit_and
std::bit_and< T > bit_and
Definition:
functional.hpp:20
sycl::_V1::bit_xor
std::bit_xor< T > bit_xor
Definition:
functional.hpp:22
sycl::_V1::bit_or
std::bit_or< T > bit_or
Definition:
functional.hpp:21
sycl
Definition:
access.hpp:18
include
sycl
ext
intel
esimd
native
common.hpp
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