#[repr(u32)]pub enum ppc_mem_instr_origin_t {
Show 51 variants
Normal_Load_Store = 0,
Caching_Inhibited = 1,
Instr_Multiple = 2,
Instr_String = 3,
Instr_Altivec_Element = 4,
Instr_dcbt = 5,
Instr_dcbst = 6,
Instr_dcbtst = 7,
Instr_dcbi = 8,
Instr_dcbf = 9,
Instr_dcbfl = 10,
Instr_dcba = 11,
Instr_dcbz = 12,
Instr_icbi = 13,
Instr_dst = 14,
Instr_dstt = 15,
Instr_dstst = 16,
Instr_dststt = 17,
Instr_dcblc_l1 = 18,
Instr_dcblc_l2 = 19,
Instr_dcbtls_l1 = 20,
Instr_dcbtls_l2 = 21,
Instr_dcbtstls_l1 = 22,
Instr_dcbtstls_l2 = 23,
Instr_icblc_l1 = 24,
Instr_icblc_l2 = 25,
Instr_icbtls_l1 = 26,
Instr_icbtls_l2 = 27,
Instr_lwarx = 28,
Instr_stwcx = 29,
Instr_ldarx = 30,
Instr_stdcx = 31,
Instr_lq = 32,
Instr_stq = 33,
Instr_sync = 34,
Instr_eieio = 35,
Instr_ecowx = 36,
Instr_eciwx = 37,
Instr_tlbie = 38,
Instr_tlbsync = 39,
Instr_isync = 40,
Instr_lfdp = 41,
Instr_stfdp = 42,
Instr_spe = 43,
Instr_dcbal = 44,
Instr_dcblc_pc = 45,
Instr_dcbtls_pc = 46,
Instr_dcbtstls_pc = 47,
Instr_icblc_pc = 48,
Instr_icbtls_pc = 49,
Instr_Fpu = 50,
}
Expand description
Variants§
Normal_Load_Store = 0
Normal load or store instructions
Caching_Inhibited = 1
No data touched by the load/store will be placed in cache
Instr_Multiple = 2
load/store multiple
Instr_String = 3
load/store string
Instr_Altivec_Element = 4
Altivec load/store element
Instr_dcbt = 5
data cache block touch
Instr_dcbst = 6
data cache block store
Instr_dcbtst = 7
data cache block touch for store
Instr_dcbi = 8
data cache block invalidate
Instr_dcbf = 9
data cache block flush
Instr_dcbfl = 10
data cache block flush local
Instr_dcba = 11
data cache block allocate
Instr_dcbz = 12
data cache block to zero
Instr_icbi = 13
instruction cache block invalidate
Instr_dst = 14
data stream touch
Instr_dstt = 15
data stream touch transient
Instr_dstst = 16
data stream touch for store
Instr_dststt = 17
data stream touch for store transient
Instr_dcblc_l1 = 18
data cache block lock clear (L1)
Instr_dcblc_l2 = 19
data cache block lock clear (L2)
Instr_dcbtls_l1 = 20
data cache block touch and lock set (L1)
Instr_dcbtls_l2 = 21
data cache block touch and lock set (L1)
Instr_dcbtstls_l1 = 22
data cache block touch for store and lock set (L1)
Instr_dcbtstls_l2 = 23
data cache block touch for store and lock set (L1)
Instr_icblc_l1 = 24
instruction cache block clear (L1)
Instr_icblc_l2 = 25
instruction cache block clear (L2)
Instr_icbtls_l1 = 26
instruction cache block touch and lock set (L1)
Instr_icbtls_l2 = 27
instruction cache block touch and lock set (L1)
Instr_lwarx = 28
Other loads/stores or cache affecting instructions
Instr_stwcx = 29
Other loads/stores or cache affecting instructions
Instr_ldarx = 30
Other loads/stores or cache affecting instructions
Instr_stdcx = 31
Other loads/stores or cache affecting instructions
Instr_lq = 32
Other loads/stores or cache affecting instructions
Instr_stq = 33
Other loads/stores or cache affecting instructions
Instr_sync = 34
Other cache affecting instructions
Instr_eieio = 35
Other cache affecting instructions
Instr_ecowx = 36
Other cache affecting instructions
Instr_eciwx = 37
Other cache affecting instructions
Instr_tlbie = 38
Other cache affecting instructions
Instr_tlbsync = 39
Other cache affecting instructions
Instr_isync = 40
Other cache affecting instructions
Instr_lfdp = 41
Load Floating point Double Pair
Instr_stfdp = 42
Store Floating point Double Pair
Instr_spe = 43
Instr_dcbal = 44
Obsolete - use Instr_dcba.
Instr_dcblc_pc = 45
data cache block lock clear
Instr_dcbtls_pc = 46
data cache block touch and lock set
Instr_dcbtstls_pc = 47
data cache block touch for store and lock set
Instr_icblc_pc = 48
instruction cache block clear
Instr_icbtls_pc = 49
instruction cache block touch and lock set
Instr_Fpu = 50
Load/store from FPU unit
Trait Implementations§
source§impl Clone for ppc_mem_instr_origin_t
impl Clone for ppc_mem_instr_origin_t
source§fn clone(&self) -> ppc_mem_instr_origin_t
fn clone(&self) -> ppc_mem_instr_origin_t
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source
. Read moresource§impl Debug for ppc_mem_instr_origin_t
impl Debug for ppc_mem_instr_origin_t
source§impl Hash for ppc_mem_instr_origin_t
impl Hash for ppc_mem_instr_origin_t
source§impl Ord for ppc_mem_instr_origin_t
impl Ord for ppc_mem_instr_origin_t
source§fn cmp(&self, other: &ppc_mem_instr_origin_t) -> Ordering
fn cmp(&self, other: &ppc_mem_instr_origin_t) -> Ordering
1.21.0 · source§fn max(self, other: Self) -> Selfwhere
Self: Sized,
fn max(self, other: Self) -> Selfwhere
Self: Sized,
source§impl PartialEq for ppc_mem_instr_origin_t
impl PartialEq for ppc_mem_instr_origin_t
source§impl PartialOrd for ppc_mem_instr_origin_t
impl PartialOrd for ppc_mem_instr_origin_t
impl Copy for ppc_mem_instr_origin_t
impl Eq for ppc_mem_instr_origin_t
impl StructuralPartialEq for ppc_mem_instr_origin_t
Auto Trait Implementations§
impl Freeze for ppc_mem_instr_origin_t
impl RefUnwindSafe for ppc_mem_instr_origin_t
impl Send for ppc_mem_instr_origin_t
impl Sync for ppc_mem_instr_origin_t
impl Unpin for ppc_mem_instr_origin_t
impl UnwindSafe for ppc_mem_instr_origin_t
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)