Enum simics_api_sys::bindings::pcie_message_type_t

#[repr(i32)]
pub enum pcie_message_type_t {
    PCIE_ATS_Invalidate = 1,
    PCIE_PRS_Request = 4,
    PCIE_PRS_Response = 5,
    PCIE_Latency_Tolerance_Reporting = 16,
    PCIE_Optimized_Buffer_Flush_Fill = 18,
    PCIE_Msg_Assert_INTA = 32,
    PCIE_Msg_Assert_INTB = 33,
    PCIE_Msg_Assert_INTC = 34,
    PCIE_Msg_Assert_INTD = 35,
    PCIE_Msg_Deassert_INTA = 36,
    PCIE_Msg_Deassert_INTB = 37,
    PCIE_Msg_Deassert_INTC = 38,
    PCIE_Msg_Deassert_INTD = 39,
    PCIE_PM_Active_State_Nak = 20,
    PCIE_PM_PME = 24,
    PCIE_PM_Turn_Off = 25,
    PCIE_PM_PME_TO_Ack = 27,
    PCIE_ERR_COR = 48,
    PCIE_ERR_NONFATAL = 49,
    PCIE_ERR_FATAL = 51,
    PCIE_Unlock = 0,
    PCIE_Set_Slot_Power_Limit = 80,
    PCIE_Precision_Time_Measurement = 82,
    PCIE_HP_Power_Indicator_On = 69,
    PCIE_HP_Power_Indicator_Blink = 71,
    PCIE_HP_Power_Indicator_Off = 68,
    PCIE_HP_Attention_Button_Pressed = 72,
    PCIE_HP_Attention_Indicator_On = 65,
    PCIE_HP_Attention_Indicator_Blink = 67,
    PCIE_HP_Attention_Indicator_Off = 64,
    PCIE_Vendor_Defined_Type_0 = 126,
    PCIE_Vendor_Defined_Type_1 = 127,
    PCIE_DLL_Link_Down = -1,
    PCIE_DLL_Link_Up = -2,
}

Variants

PCIE_ATS_Invalidate = 1

Address Translation

PCIE_PRS_Request = 4

Address Translation

PCIE_PRS_Response = 5

Address Translation

PCIE_Latency_Tolerance_Reporting = 16

Address Translation

PCIE_Optimized_Buffer_Flush_Fill = 18

Address Translation

PCIE_Msg_Assert_INTA = 32

INTx emulation

PCIE_Msg_Assert_INTB = 33

INTx emulation

PCIE_Msg_Assert_INTC = 34

INTx emulation

PCIE_Msg_Assert_INTD = 35

INTx emulation

PCIE_Msg_Deassert_INTA = 36

INTx emulation

PCIE_Msg_Deassert_INTB = 37

INTx emulation

PCIE_Msg_Deassert_INTC = 38

INTx emulation

PCIE_Msg_Deassert_INTD = 39

INTx emulation

PCIE_PM_Active_State_Nak = 20

Power Management

PCIE_PM_PME = 24

Power Management

PCIE_PM_Turn_Off = 25

Power Management

PCIE_PM_PME_TO_Ack = 27

Power Management

PCIE_ERR_COR = 48

Error Messages

PCIE_ERR_NONFATAL = 49

Error Messages

PCIE_ERR_FATAL = 51

Error Messages

PCIE_Unlock = 0

Locked Transaction

PCIE_Set_Slot_Power_Limit = 80

Slot Power Limit

PCIE_Precision_Time_Measurement = 82

Slot Power Limit

PCIE_HP_Power_Indicator_On = 69

Hot Plug Messages

PCIE_HP_Power_Indicator_Blink = 71

Hot Plug Messages

PCIE_HP_Power_Indicator_Off = 68

Hot Plug Messages

PCIE_HP_Attention_Button_Pressed = 72

Hot Plug Messages

PCIE_HP_Attention_Indicator_On = 65

Hot Plug Messages

PCIE_HP_Attention_Indicator_Blink = 67

Hot Plug Messages

PCIE_HP_Attention_Indicator_Off = 64

Hot Plug Messages

PCIE_Vendor_Defined_Type_0 = 126

Hot Plug Messages

PCIE_Vendor_Defined_Type_1 = 127

Hot Plug Messages

PCIE_DLL_Link_Down = -1

Data Link Layer (virtual) Messages

NOTE: these messages only exist on Simics simulator, as they are normally part of the Data Link Layer which is below the level of abstraction for Simics PCIe models

According to PCIe rev 2.0, when a target receives a message that it does not recognize or support, except for the “Vendor Defined Type 1” message, it should treat the request as an “Unsupported Request” and report it accordingly (see sec 2.3.1 for reference).

Hence models that comply with rev 2.0 must be updated to either

1. handle these messages or 2) ignore these messages.

Ideally we would like to use a new pcie_link interface to transmit this information - see bug 17849 for more info.

PCIE_DLL_Link_Up = -2

Data Link Layer (virtual) Messages

NOTE: these messages only exist on Simics simulator, as they are normally part of the Data Link Layer which is below the level of abstraction for Simics PCIe models

According to PCIe rev 2.0, when a target receives a message that it does not recognize or support, except for the “Vendor Defined Type 1” message, it should treat the request as an “Unsupported Request” and report it accordingly (see sec 2.3.1 for reference).

Hence models that comply with rev 2.0 must be updated to either

1. handle these messages or 2) ignore these messages.

Ideally we would like to use a new pcie_link interface to transmit this information - see bug 17849 for more info.

Implementations

impl pcie_message_type_t

pub const PCIE_Locked_Transaction: pcie_message_type_t = pcie_message_type_t::PCIE_Unlock

Trait Implementations

impl Clone for pcie_message_type_t

fn clone(&self) -> pcie_message_type_t

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for pcie_message_type_t

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for pcie_message_type_t

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl Ord for pcie_message_type_t

fn cmp(&self, other: &pcie_message_type_t) -> Ordering

This method returns an Ordering between self and other.

fn max(self, other: Self) -> Self

where Self: Sized,

Compares and returns the maximum of two values.

fn min(self, other: Self) -> Self

where Self: Sized,

Compares and returns the minimum of two values.

fn clamp(self, min: Self, max: Self) -> Self

where Self: Sized + PartialOrd,

Restrict a value to a certain interval.

impl PartialEq for pcie_message_type_t

fn eq(&self, other: &pcie_message_type_t) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl PartialOrd for pcie_message_type_t

fn partial_cmp(&self, other: &pcie_message_type_t) -> Option<Ordering>

This method returns an ordering between self and other values if one exists.

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator.

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator.

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator.

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator.

impl Copy for pcie_message_type_t

impl Eq for pcie_message_type_t

impl StructuralPartialEq for pcie_message_type_t