IndexGate constructor

IndexGate(
  1. Logic original,
  2. Logic index
)

Constructs a two-input bit index gate for an arbitrary custom functional implementation.

The signal will be indexed by index as an output. Module is in-lined as SystemVerilog, it will use originalindex, where target is index's int value When, the original has width '1', index is ignored in the generated SystemVerilog.

Implementation

IndexGate(Logic original, Logic index) : super() {
  _originalName = 'original_${original.name}';
  _indexName = Naming.unpreferredName('index_${index.name}');
  _selectionName =
      Naming.unpreferredName('${original.name}_indexby_${index.name}');

  addInput(_originalName, original, width: original.width);
  addInput(_indexName, index, width: index.width);
  addOutput(_selectionName)
      .makeUnassignable(reason: 'Output of a gate $this cannot be assigned.');

  _setup();
}