BusSubset constructor Null safety

BusSubset(
  1. Logic bus,
  2. int startIndex,
  3. int endIndex,
  4. {String name = 'bussubset'}
)

Constructs a Module that accesses a subset from bus which ranges from startIndex to endIndex (inclusive of both). When, bus has a width of '1', startIndex and endIndex are ignored in the generated SystemVerilog.

Implementation

BusSubset(Logic bus, this.startIndex, this.endIndex,
    {super.name = 'bussubset'}) {
  // If a converted index value is still -ve then it's an Index out of bounds
  // on a Logic Bus
  if (startIndex < 0 || endIndex < 0) {
    throw Exception(
        'Start ($startIndex) and End ($endIndex) must be greater than or '
        'equal to 0.');
  }
  // If the +ve indices are more than Logic bus width, Index out of bounds
  if (endIndex > bus.width - 1 || startIndex > bus.width - 1) {
    throw Exception(
        'Index out of bounds, indices $startIndex and $endIndex must be less'
        ' than ${bus.width}');
  }

  // original name can't be unpreferred because you cannot do a bit slice
  // on expressions in SystemVerilog, and other expressions could have
  // been in-lined
  _original = 'original_${bus.name}';

  _subset =
      Module.unpreferredName('subset_${endIndex}_${startIndex}_${bus.name}');

  addInput(_original, bus, width: bus.width);
  final newWidth = (endIndex - startIndex).abs() + 1;
  addOutput(_subset, width: newWidth);

  // so that people can't do a slice assign, not (yet?) implemented
  subset.makeUnassignable();

  _setup();
}