BusSubset constructor

BusSubset(
  1. Logic bus,
  2. int startIndex,
  3. int endIndex,
  4. {String name = 'bussubset'}
)

Constructs a Module that accesses a subset from bus which ranges from startIndex to endIndex (inclusive of both). When, bus has a width of '1', startIndex and endIndex are ignored in the generated SystemVerilog.

Implementation

BusSubset