AsyncFifo class

An asynchronous FIFO for safely passing data between two clock domains.

The AsyncFifo implements a dual-clock FIFO that allows data to be written in one clock domain and read in another, completely independent clock domain. This is essential for designs that need to transfer data between different clock frequencies or phases.

Key Features:

• Independent write and read clock domains
• Gray-coded pointers for safe clock domain crossing
• Proper synchronization to prevent metastability
• Full/empty flag generation
• Data integrity across clock domains

Implementation Details:

• Uses Gray code for pointer synchronization (only 1 bit changes at a time)
• Multi-stage synchronizers for crossing pointer values
• Write pointers synchronized to read domain for empty detection
• Read pointers synchronized to write domain for full detection

Important Notes:

• The depth must be a power of 2 for proper Gray code wrapping
• Full/empty flags have synchronization latency (typically 2 cycles)
• FIFO appears empty for a few cycles after reset due to sync latency

Example:

final asyncFifo = AsyncFifo(
  writeClk: wrClk,
  readClk: rdClk,
  writeReset: wrRst,
  readReset: rdRst,
  writeEnable: wrEn,
  writeData: wrData,
  readEnable: rdEn,
  depth: 16,
);