AsyncFifo constructor

AsyncFifo({
  1. required Logic writeClk,
  2. required Logic readClk,
  3. required Logic writeReset,
  4. required Logic readReset,
  5. required Logic writeEnable,
  6. required Logic writeData,
  7. required Logic readEnable,
  8. required int depth,
  9. int syncStages = 2,
  10. String name = 'async_fifo',
})

Constructs an AsyncFifo with the specified parameters.

  • writeClk: Clock for the write domain.
  • readClk: Clock for the read domain.
  • writeReset: Reset signal for the write domain.
  • readReset: Reset signal for the read domain.
  • writeEnable: Write enable signal (active high).
  • writeData: Data to write into the FIFO.
  • readEnable: Read enable signal (active high).
  • depth: Number of entries in the FIFO (must be power of 2).
  • syncStages: Number of synchronizer stages (default: 2).

Implementation

AsyncFifo({
  required Logic writeClk,
  required Logic readClk,
  required Logic writeReset,
  required Logic readReset,
  required Logic writeEnable,
  required Logic writeData,
  required Logic readEnable,
  required this.depth,
  this.syncStages = 2,
  super.name = 'async_fifo',
})  : dataWidth = writeData.width,
      _addrWidth = log2Ceil(depth),
      super(definitionName: 'AsyncFifo_D${depth}_W${writeData.width}') {
  if (depth <= 0) {
    throw RohdHclException('Depth must be at least 1.');
  }

  if (depth & (depth - 1) != 0) {
    throw RohdHclException('Depth must be a power of 2, but got $depth.'
        ' Use depths like 2, 4, 8, 16, 32, etc.');
  }

  // Add inputs
  addInput('writeClk', writeClk);
  addInput('readClk', readClk);
  addInput('writeReset', writeReset);
  addInput('readReset', readReset);
  addInput('writeEnable', writeEnable);
  addInput('writeData', writeData, width: dataWidth);
  addInput('readEnable', readEnable);

  // Add outputs
  addOutput('readData', width: dataWidth);
  addOutput('full');
  addOutput('empty');

  _buildLogic();
}