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enum | sycl::_V1::ext::intel::esimd::native::lsc::atomic_op : uint8_t {
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::inc = 0x08,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::dec = 0x09,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::load = 0x0a,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::store = 0x0b,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::add = 0x0c,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::sub = 0x0d,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::smin = 0x0e,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::smax = 0x0f,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::umin = 0x10,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::umax = 0x11,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::cmpxchg = 0x12,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fadd = 0x13,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fsub = 0x14,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fmin = 0x15,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fmax = 0x16,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::fcmpxchg = 0x17,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::bit_and = 0x18,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::bit_or = 0x19,
sycl::_V1::ext::intel::esimd::native::lsc::atomic_op::bit_xor = 0x1a
} |
| LSC atomic operation codes. More...
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