sample-risc-core

Description

Sample RISC core.

Interfaces Implemented

conf_object, log_object, context_handler, processor_info_v2, processor_info, int_register, exception, processor_cli, opcode_info

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Commands for this class

info – print information about the object
status – print status of the object

Commands for interface context_handler

set-context – set the current context of a CPU

Commands for interface processor_info

debug – get debug object
disable – switch processor off
disassemble – disassemble instructions
enable – switch processor on
enabled – get enable status
load-binary – load binary (executable) file into memory
logical-to-physical – translate logical address to physical
print-processor-registers – print cpu registers
read-reg – read a register
set-pc – set the program counter
write-reg – write to register
x – examine raw memory contents

Commands for interface exception

bp-break-exception – set break on exception
bp-run-until-exception – run until specified exception occurs
bp-trace-exception – enable tracing of exceptions
bp-wait-for-exception – wait for specified exception
break-exception – deprecated break on CPU exceptions
list-exceptions – list exceptions on a processor
trace-exception – deprecated trace exceptions
unbreak-exception – deprecated break on CPU exceptions
untrace-exception – deprecated trace exceptions
wait-for-exception – deprecated wait until a processor exception happens

Attributes

sample_risc: Required attribute; read/write access; type: o
Cosimulator object.
physical_memory_space: Required attribute; read/write access; type: o
Physical memory space.
core_enabled: Optional attribute; read/write access; type: b
Core state: enabled.
idle_cycles: Optional attribute; read/write access; type: i
Number of idle cycles.
stallable_memops: Optional attribute; read/write access; type: b
If true, read and write transactions will be issued as stallable operations.
current_context: Pseudo attribute; read/write access; type: o|n
Current context object
processor_number: Optional attribute; read/write access; type: i
Simics internal number for an instance of the 'processor_info' interface. Each instance must have a unique number. This attribute can only be set as part of an initial configuration.
registers: Optional attribute; read/write access; type: [i*]
The registers.
freq_mhz: Optional attribute; read/write access; type: f
The frequency in MHz for the core.
r0: Optional attribute; read/write access; type: i
r0
r1: Optional attribute; read/write access; type: i
r1
r2: Optional attribute; read/write access; type: i
r2
r3: Optional attribute; read/write access; type: i
r3
r4: Optional attribute; read/write access; type: i
r4
r5: Optional attribute; read/write access; type: i
r5
r6: Optional attribute; read/write access; type: i
r6
r7: Optional attribute; read/write access; type: i
r7
r8: Optional attribute; read/write access; type: i
r8
r9: Optional attribute; read/write access; type: i
r9
r10: Optional attribute; read/write access; type: i
r10
r11: Optional attribute; read/write access; type: i
r11
r12: Optional attribute; read/write access; type: i
r12
r13: Optional attribute; read/write access; type: i
r13
r14: Optional attribute; read/write access; type: i
r14
r15: Optional attribute; read/write access; type: i
r15
pc: Optional attribute; read/write access; type: i
pc
msr: Optional attribute; read/write access; type: i
msr

Provided By

sample-risc