sample-risc

Description

The sample RISC (Reduced Instructions Set Computer/Cosimulator).

Interfaces Implemented

conf_object, log_object, simulator_cache, breakpoint_change, direct_memory_update, stall, execute, cycle, event_delta, frequency, step, frequency_listener

Notifiers

cell-change: Notifier that is triggered after the object's cell was changed.
frequency-change: Notifier that is triggered when frequency changes. New frequency can be read via the frequency interface of the object.
object-delete: Notifier that is triggered just before Simics object is deleted.
queue-change: Notifier that is triggered after the object's clock was changed. New clock can be obtained with the SIM_object_clock function.

Port Objects

vtime: vtime – event handler
vtime.cycles: cycle-counter – cycle queue
vtime.ps: ps-clock – event queue (ps)

Commands for this class

info – print information about the object
status – print status of the object

Commands for interface cycle

bp-break-cycle – set cycle breakpoint
bp-break-time – set time breakpoint
bp-run-until-cycle – run until specified cycle
bp-run-until-time – run until specified time
bp-trace-cycle – enable tracing of cycle points
bp-trace-time – enable tracing of time points
bp-wait-for-cycle – wait for specified cycle
bp-wait-for-time – wait for specified time
cycle-break – deprecated set cycle breakpoint
cycle-break-absolute – deprecated set absolute cycle breakpoint
print-time – print number of steps and cycles executed
wait-for-cycle – deprecated wait until reaching cycle
wait-for-time – deprecated wait until reaching a specified time

Commands for interface step

bp-break-step – set step breakpoint
bp-run-until-step – run until specified step
bp-trace-step – enable tracing of step points
bp-wait-for-step – wait for specified step
force-step-instruction – step instructions while other processors stall
step-break – deprecated set time breakpoint
step-break-absolute – deprecated set step breakpoints
wait-for-step – deprecated wait until reaching step

Attributes

current_risc_core: Required attribute; read/write access; type: o
Currently active core used for commands that normally target the current processor.
cached_pages: Pseudo attribute; read-only access; type: [[oiii]*]
Cached pages; for debugging/testing purposes only
do_not_schedule: Optional attribute; read/write access; type: b
Set to TRUE to prevent this object from being scheduled by the cell.
cycles: Optional attribute; read/write access; type: i
Time measured in cycles from machine start.
time_queue: Optional attribute; read/write access; type: [[osaii]*]
((object, evclass, value, slot, step)*).
cell: Optional attribute; read/write access; type: o|n
Cell
steps: Optional attribute; read/write access; type: i
Time measured in steps from machine start.
step_queue: Optional attribute; read/write access; type: [[osaii]*]
((object, evclass, value, slot, step)*).
freq_mhz: Pseudo attribute; read/write access; type: i|f
Processor clock frequency in MHz.
frequency: Optional attribute; read/write access; type: [ii]|o|[os]
Processor clock frequency in Hz, as a rational number [numerator, denominator].

Provided By

sample-risc