PCIe Modeling Library

Supported Hardware Features

Simics PCIe modeling library supports up to PCI Express Base Specification Revision 6.0. Some of the features it supports with little or no modeling effort are:

• Sending and receiving PCIe Messages
• Upstream and downstream I/O and Memory operations
• Legacy PCI Interrupts
• Message Signalled Interrupts (MSI)
• Message Signalled Interrupts X (MSI-X)
• Resizable BARs (RBAR)
• Virtual Function Resizable BARs (VFRBAR)
• Single Root I/O Virtualization (SR-IOV)
• Address Translation Service (ATS)

Simics PCIe Abstraction

PCIe is simulated in Simics on a functional level, which means that models typically operate slightly above the Transaction Layer. Simics does not simulate individual TLPs, it simulates relevant parts of the TLP and conveys the information along the route to the target destination.

A Transaction Layer Package (TLP) in PCIe comes in four different types: Config, Memory, I/O, and Message. All of these are issued using the transaction_t data structure. The various bits of information required to complete an operation (PASID, RequesterID, etc.) are attached to the transaction_t as atoms.

• Quickstart
• High level design
• PCIe in DML
• DML template reference