Processor Model Integration Guide

This document describes the API used to implement models of processors in Simics. Simics handles the simulation framework, including the user interfaces, standardized APIs, plug-in administration, and commonly used utilities and resources. The processor models use and implement the standardized APIs, which allows mixing simulation models and creating a uniform interface to the user.

The processor API is the part of the API that gives a model to get control over simulator scheduling. It includes processor specific interfaces to enable standard functions and commands for the processor models as well as efficient memory interfaces to allow fast simulation. The most important interfaces are covered in this document, for the other interfaces please refer to the API Reference Manual.

Depending on use, the processors should implement and use different parts of the interfaces described.

A number of areas that a processor model may support can be identified as follows:

Simulation scheduling

There must be basic support for advancing the simulation. This support must be present for any fast functional processor model. Cycle driven models may be designed using the built-in clock class that handles the scheduling interaction with the framework.

Direct Access to Memory

Interfaces used to cache pointers to memory, allowing accesses to be carried out without involving the API.

Inspection and control of processor models

As processors are very visible to the user of the simulator, there are several standardized ways for the user to access and control a processor. To support these, the processor models in turn have to implement interfaces and trigger haps.

Breakpoints

The processor model is fully responsible for triggering virtual address breakpoints. For physical address breakpoints, the processor model needs to check if ranges mapped with direct memory access contain breakpoints and then either request more fine grained regions of memory without breakpoints or fall back to explicit memory operations, where the explicit memory operations will handle breakpoints if they happen to match.

Simulation of models

Covers the mechanisms used to communicate between processors and devices.

Like any other model, processor models should be written to integrate well into the Simics environment. See the Simics Model Development Checklist section for a good checklist to follow when designing and implementing the model. See also the Simics User’s Guide for more information about the features discussed in this document.

How to configure a system and create start scripts is described in System Configurations in Model Builder User’s Guide. Example system configurations can be found in [simics]/targets/cosim/.

• 1 Processor Scheduling Examples
• 2 Simulation Scheduling
• 3 Direct Access to Memory
• 4 Controlling and Inspecting Processor State
• 5 Breakpoints
• 6 Simics Environment Interaction
• 7 Simics API Functions
• 8 Miscellaneous Remarks