4 Controlling and Inspecting Processor State

The processor state can be controlled and inspected using commands or GUI controls. This chapter describes the interfaces, haps, and breakpoint functionality required for supporting this.

4.1 Commands

Several generic Simics commands work automatically when standard interfaces are implemented. How the interfaces map onto objects depends on how the model is designed, for example the type of models described in Chapter 1.

4.2 Interfaces

This section lists the interfaces that can be implemented by the processor model to enable certain Simics features. They are not required, but implementing them will allow user defined processor models to support the same generic feature set as Simics standard processor models. If you intend to plug your model into an existing Simics-provided platform, then many of these interfaces are actually required for such a platform to function.

• processor_info_v2
• processor_cli
• processor_gui
• step
• step_cycle_ratio
• stall
• int_register
• decoder
• exception
  The exception interface is used together with the Core_Exception hap to enable inspection abilities for triggered exceptions.
• context_handler
• exec_trace
• opcode_info
• virtual_data_breakpoint
• virtual_instruction_breakpoint
• describe_registers

4.3 Using Haps

A hap is an event or occurrence in Simics with some specific semantic meaning, either related to the target or to the internals of the simulator. Haps can for instance be used by the cosimulator to trigger events on control register reads or writes.

The cosimulator calls one of the SIM_c_hap_occurred... functions to trigger a hap. The Simics User’s Guide document describes how to get a callback when a hap is triggered.

To be fully compatible with regular Simics CPU models, a cosimulator should trigger the following haps:

• Core_Exception
• Core_Exception_Return
• Core_Asynchronous_Trap
• Core_Control_Register_Read
• Core_Control_Register_Write
• Core_External_Interrupt
• Core_Sync_Instruction
• Core_Mode_Switch (x86 processors only)
• Core_Interrupt_Status (x86 processors only)
• Core_Magic_Instruction
• Core_Mode_Change

Details about the haps can be found in the Simics Reference Manual, or online with the list-haps command. The sample-risc module in [simics]/src/extensions/sample-risc/ contains example code how to raise Core_Control_Register_Read and Core_Control_Register_Write haps.

The cosimulator should not trigger the following haps as they are triggered by the Simics core:

• Core_Breakpoint
• Core_Breakpoint_Memop