1 Processor Scheduling Examples 3 Direct Access to Memory
Processor Model Integration Guide  / 

2 Simulation Scheduling

This chapter lists the interfaces used for customized simulation scheduling.

2.1 Execute Interface

See execute for the documentation of the interface.

In figure 4 there is an example call-graph of Simics core and processor scheduler communication. Simics posts events on the processor’s event queues to be triggered, for instance, at the end of the allowed time window. Simics then calls the run function in the execute interface and the processor starts executing instructions. The processor which implements the event queues will after a while execute an event callback for the event posted by the Simics core in one of the event queues. The Simics core handles the event which will trigger a stop request via the stop function. Note that not all events will trigger a stop request. Having received stop, the processor model must stop the simulation as soon as possible and return to the Simics core. This is typically done as soon as the currently executing instruction is committed.

Figure 4. An example of Simics core and scheduler communication.

2.2 Other Interfaces

1 Processor Scheduling Examples 3 Direct Access to Memory