instantiationVerilog method

  1. @override
String instantiationVerilog(
  1. String instanceType,
  2. String instanceName,
  3. Map<String, String> ports
)
override

Generates custom SystemVerilog to be injected in place of a module instantiation.

The instanceType and instanceName represent the type and name, respectively of the module that would have been instantiated had it not been overridden. ports is a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog.

If a standard instantiation is desired, either return null or use SystemVerilogSynthesizer.instantiationVerilogFor with forceStandardInstantiation set to true. By default, null is returned and thus a standard instantiation is used.

Implementation

@override
String instantiationVerilog(
  String instanceType,
  String instanceName,
  Map<String, String> ports,
) {
  assert(ports.length == 3, 'Tristate buffer should have 2 inputs, 1 inout.');

  final in_ = ports[_inName]!;
  final enable = ports[_enableName]!;
  final out = ports[_outName];
  return 'assign $out = $enable ? $in_ : ${LogicValue.filled(_in.width, LogicValue.z)}; // tristate';
}