instantiationVerilog method

  1. @override
String instantiationVerilog(
  1. String instanceType,
  2. String instanceName,
  3. Map<String, String> ports
)
override

Generates custom SystemVerilog to be injected in place of a module instantiation.

The instanceType and instanceName represent the type and name, respectively of the module that would have been instantiated had it not been overridden. ports is a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog.

If a standard instantiation is desired, either return null or use SystemVerilogSynthesizer.instantiationVerilogFor with forceStandardInstantiation set to true. By default, null is returned and thus a standard instantiation is used.

Implementation

@override
String instantiationVerilog(
    String instanceType, String instanceName, Map<String, String> ports) {
  assert(ports.length == 1,
      'SimpleClockGenerator has exactly one output and no inputs.');

  final clk = ports['clk']!;
  return '''
// $instanceName
initial begin
$clk = 0;
forever begin
  #${clockPeriod ~/ 2};
  $clk = ~$clk;
end
end
''';
}