inlineVerilog abstract method
Generates custom SystemVerilog to be injected in place of the output port's corresponding signal name.
The inputs
are a mapping from the Module's port names to the names of
the signals that are passed into those ports in the generated
SystemVerilog. It will only contain inputs and inOuts, as there
should only be one output which is driven by the expression.
The output will be appropriately wrapped with parentheses to guarantee proper order of operations.
Implementation
String inlineVerilog(Map<String, String> inputs);