instantiationVerilog method

  1. @override
String instantiationVerilog(
  1. String instanceType,
  2. String instanceName,
  3. Map<String, String> ports
)
override

Generates custom SystemVerilog to be injected in place of a module instantiation.

The instanceType and instanceName represent the type and name, respectively of the module that would have been instantiated had it not been overridden. ports is a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog.

If a standard instantiation is desired, either return null or use SystemVerilogSynthesizer.instantiationVerilogFor with forceStandardInstantiation set to true. By default, null is returned and thus a standard instantiation is used.

Implementation

@override
String instantiationVerilog(
    String instanceType, String instanceName, Map<String, String> ports) {
  var expectedInputs = 2;
  if (_en != null) {
    expectedInputs++;
  }
  if (_reset != null) {
    expectedInputs++;
  }
  if (_resetValuePort != null) {
    expectedInputs++;
  }

  assert(ports.length == expectedInputs + 1,
      'FlipFlop has exactly $expectedInputs inputs and one output.');

  final clk = ports[_clkName]!;
  final d = ports[_dName]!;
  final q = ports[_qName]!;
  final en = _en != null ? ports[_enName]! : null;
  final reset = _reset != null ? ports[_resetName]! : null;

  final triggerString = [
    clk,
    if (reset != null && asyncReset) reset,
  ].map((e) => 'posedge $e').join(' or ');

  final svBuffer = StringBuffer('always_ff @($triggerString) ');

  if (_reset != null) {
    final resetValueString = _resetValuePort != null
        ? ports[_resetValueName]!
        : _resetValueConst.toString();
    svBuffer.write('if(${reset!}) $q <= $resetValueString; else ');
  }

  if (_en != null) {
    svBuffer.write('if(${en!}) ');
  }

  svBuffer.write('$q <= $d;  // $instanceName');

  return svBuffer.toString();
}