inlineVerilog method

  1. @override
String inlineVerilog(
  1. Map<String, String> inputs
)
override

Generates custom SystemVerilog to be injected in place of the output port's corresponding signal name.

The inputs are a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog. It will only contain inputs and inOuts, as there should only be one output (named resultSignalName) which is driven by the expression.

The output will be appropriately wrapped with parentheses to guarantee proper order of operations.

Implementation

@override
String inlineVerilog(Map<String, String> inputs) {
  assert(inputs.length == 1 || (inputs.length == 2 && _isNet),
      'BusSubset has exactly one input, but saw $inputs.');

  final a = inputs[_originalName]!;

  assert(!a.contains(_expressionRegex),
      'Inputs to bus swizzle cannot contain any expressions.');

  // When, input width is 1, ignore startIndex and endIndex
  if (original.width == 1) {
    return a;
  }

  // SystemVerilog doesn't allow reverse-order select to reverse a bus,
  // so do it manually
  if (startIndex > endIndex) {
    final swizzleContents =
        List.generate(startIndex - endIndex + 1, (i) => '$a[${endIndex + i}]')
            .join(',');
    return '{$swizzleContents}';
  }

  final sliceString =
      startIndex == endIndex ? '[$startIndex]' : '[$endIndex:$startIndex]';
  return '$a$sliceString';
}