inlineVerilog method

  1. @override
String inlineVerilog(
  1. Map<String, String> inputs

Generates custom SystemVerilog to be injected in place of the output port's corresponding signal name.

The inputs are a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog.

The output will be appropriately wrapped with parentheses to guarantee proper order of operations.


String inlineVerilog(Map<String, String> inputs) {
  if (inputs.length != 1) {
    throw Exception('BusSubset has exactly one input, but saw $inputs.');
  final a = inputs[_original]!;

      'Inputs to bus swizzle cannot contain any expressions.');

  // When, input width is 1, ignore startIndex and endIndex
  if (original.width == 1) {
    return a;

  // SystemVerilog doesn't allow reverse-order select to reverse a bus,
  // so do it manually
  if (startIndex > endIndex) {
    final swizzleContents =
        List.generate(startIndex - endIndex + 1, (i) => '$a[${endIndex + i}]')
    return '{$swizzleContents}';

  final sliceString =
      startIndex == endIndex ? '[$startIndex]' : '[$endIndex:$startIndex]';
  return '$a$sliceString';