inlineVerilog method

  1. @override
String inlineVerilog(
  1. Map<String, String> inputs

Generates custom SystemVerilog to be injected in place of the output port's corresponding signal name.

The inputs are a mapping from the Module's port names to the names of the signals that are passed into those ports in the generated SystemVerilog.

The output will be appropriately wrapped with parentheses to guarantee proper order of operations.


String inlineVerilog(Map<String, String> inputs) {
  if (inputs.length != 2) {
    throw Exception('Gate has exactly two inputs.');
  final in_ = inputs[_inName]!;
  final shiftAmount = inputs[_shiftAmountName]!;

  String signWrap(String original) =>
      signed ? '\$signed($original)' : original;

  final aStr = signWrap(in_);

  final shiftStr = '$aStr $_opStr $shiftAmount';

  // In case of signed, wrap in {} to make it self-determined.
  return signed ? '{$shiftStr}' : shiftStr;