FloatingPointMultiplierSimple<FpTypeIn extends FloatingPoint, FpTypeOut extends FloatingPoint> class

A multiplier module for FloatingPoint logic.

Inheritance

Constructors

FloatingPointMultiplierSimple.new(FpTypeIn a, FpTypeIn b, {Logic? clk, Logic? reset, Logic? enable, FpTypeOut? outProduct, FloatingPointRoundingMode roundingMode = FloatingPointRoundingMode.truncate, Multiplier multGen(Logic a, Logic b, {Logic? clk, Logic? enable, String name, Logic? reset}) = NativeMultiplier.new, PriorityEncoder priorityGen(Logic bitVector, {bool generateValid, String name}) = RecursiveModulePriorityEncoder.new, String name = 'floating_point_multiplier', bool reserveName = false, bool reserveDefinitionName = false, String? definitionName})
Multiply two FloatingPoint numbers a and b, returning result in product FloatingPoint.

Properties

a ↔ FpTypeIn
The multiplicand a.
latefinalinherited
b ↔ FpTypeIn
The multiplier b.
latefinalinherited
clk ↔ Logic?
The clk : if a non-null clock signal is passed in, a pipestage is added to the adder to help optimize frequency.
latefinalinherited
definitionName → String
The definition name of this Module used when instantiating instances in generated code.
no setterinherited
enable ↔ Logic?
Optional enable, used only if a clk is not null to enable the pipeline flops.
latefinalinherited
exponentWidth ↔ int
Width of the output exponent field.
latefinalinherited
hasBuilt → bool
Indicates whether this Module has had the build method called on it.
no setterinherited
hashCode → int
The hash code for this object.
no setterinherited
inOuts → Map<String, Logic>
A map from inOut port names to this Module to corresponding Logic signals.
no setterinherited
inputs → Map<String, Logic>
A map from input port names to this Module to corresponding Logic signals.
no setterinherited
internalProduct ↔ FpTypeOut
The internal FloatingPoint logic in which to store the product of the multiplication.
latefinalinherited
internalSignals → Iterable<Logic>
An Iterable of all Logics contained within this Module which are not an input or output port of this Module.
no setterinherited
mantissaWidth ↔ int
Width of the output mantissa field.
latefinalinherited
name → String
The name of this Module.
finalinherited
outputs → Map<String, Logic>
A map from output port names to this Module to corresponding Logic signals.
no setterinherited
parent → Module?
The parent Module of this Module.
no setterinherited
product → FpTypeOut
The computed FpTypeOut product of a * b.
latefinalinherited
reserveDefinitionName → bool
If true, guarantees definitionName is maintained by a Synthesizer, or else it will fail.
finalinherited
reserveName → bool
If true, guarantees uniqueInstanceName matches name or else the build will fail.
finalinherited
reset ↔ Logic?
Optional reset, used only if a clk is not null to reset the pipeline flops.
latefinalinherited
roundingMode ↔ FloatingPointRoundingMode
The rounding mode to use for the multiplier.
latefinalinherited
runtimeType → Type
A representation of the runtime type of the object.
no setterinherited
signals → Iterable<Logic>
An Iterable of all Logics contained within this Module, including inputs, outputs, and internal signals of this Module.
no setterinherited
subModules → Iterable<Module>
An Iterable of all Modules contained within this Module.
no setterinherited
uniqueInstanceName → String
If this module has a parent, after build this will be a guaranteed unique name within its scope.
no setterinherited

Methods

addInOut(String name, Logic source, {int width = 1}) → LogicNet
Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module.
inherited
addInOutArray(String name, Logic source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an inOut LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addInput(String name, Logic source, {int width = 1}) → Logic
Registers a signal as an input to this Module and returns an input port that can be consumed.
inherited
addInputArray(String name, Logic source, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an input LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addInterfacePorts<InterfaceType extends Interface<TagType>, TagType extends Enum>(InterfaceType source, {Iterable<TagType>? inputTags, Iterable<TagType>? outputTags, Iterable<TagType>? inOutTags, String uniquify(String original)?}) → InterfaceType
Connects the source to this Module using Interface.connectIO and returns a copy of the source that can be used within this module.
inherited
addOutput(String name, {int width = 1}) → Logic
Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it.
inherited
addOutputArray(String name, {List<int> dimensions = const [1], int elementWidth = 1, int numUnpackedDimensions = 0}) → LogicArray
Registers and returns an output LogicArray port to this Module with the specified dimensions, elementWidth, and numUnpackedDimensions named name.
inherited
addPairInterfacePorts<InterfaceType extends PairInterface>(InterfaceType source, PairRole role, {String uniquify(String original)?}) → InterfaceType
Connects the source to this Module using PairInterface.pairConnectIO and returns a copy of the source that can be used within this module.
inherited
addTypedInOut<LogicType extends Logic>(String name, LogicType source) → LogicType
Registers a signal as an inOut to this Module and returns an inOut port that can be consumed inside this Module. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
inherited
addTypedInput<LogicType extends Logic>(String name, LogicType source) → LogicType
Registers a signal as an input to this Module and returns an input port that can be consumed. The type of the port will be LogicType and constructed via Logic.clone, so it is required that the source implements clone functionality that matches the type and properly updates the Logic.name as well.
inherited
addTypedOutput<LogicType extends Logic>(String name, LogicType logicGenerator({String name})) → LogicType
Registers an output to this Module and returns an output port that can be driven by this Module or consumed outside of it. The type of the port will be LogicType and constructed via logicGenerator, which must properly update the name of the generated LogicType as well.
inherited
build() → Future<void>
Builds the Module and all subModules within it.
inherited
generateSynth() → String
Returns a synthesized version of this Module.
inherited
hierarchy() → Iterable<Module>
Returns an Iterable of Modules representing the hierarchical path to this Module.
inherited
hierarchyString([int indent = 0]) → String
Returns a pretty-print String of the heirarchy of all Modules within this Module.
inherited
inOut(String name) → Logic
Accesses the Logic associated with this Modules inOut port named name.
inherited
inOutSource(String name) → Logic
The original source provided to the creation of the inOut port name via addInOut or addInOutArray.
inherited
input(String name) → Logic
Accesses the Logic associated with this Modules input port named name.
inherited
inputSource(String name) → Logic
The original source provided to the creation of the input port name via addInput or addInputArray.
inherited
isInOut(Logic signal) → bool
Returns true iff signal is the same Logic as the inOut port of this Module with the same name.
inherited
isInput(Logic signal) → bool
Returns true iff signal is the same Logic as the input port of this Module with the same name.
inherited
isOutput(Logic signal) → bool
Returns true iff signal is the same Logic as the output port of this Module with the same name.
inherited
isPort(Logic signal) → bool
Returns true iff signal is the same Logic as an input, output, or inOut port of this Module with the same name.
inherited
localFlop(Logic input) → Logic
Pipelining helper that uses the context for signals clk/enable/reset
inherited
noSuchMethod(Invocation invocation) → dynamic
Invoked when a nonexistent method or property is accessed.
inherited
output(String name) → Logic
Accesses the Logic associated with this Modules output port named name.
inherited
toString() → String
A string representation of this object.
inherited
tryInOut(String name) → Logic?
Provides the inOut named name if it exists, otherwise null.
inherited
tryInput(String name) → Logic?
Provides the input named name if it exists, otherwise null.
inherited
tryOutput(String name) → Logic?
Provides the output named name if it exists, otherwise null.
inherited

Operators

operator ==(Object other) → bool
The equality operator.
inherited